{"payload":{"feedbackUrl":"https://github.com/orgs/community/discussions/53140","repo":{"id":658404840,"defaultBranch":"main","name":"Digital-Schmitt-Trigger-Controller-System-Verilog","ownerLogin":"ayush-agarwal-0502","currentUserCanPush":false,"isFork":false,"isEmpty":false,"createdAt":"2023-06-25T16:37:27.000Z","ownerAvatar":"https://avatars.githubusercontent.com/u/86561124?v=4","public":true,"private":false,"isOrgOwned":false},"refInfo":{"name":"","listCacheKey":"v0:1687711088.0","currentOid":""},"activityList":{"items":[{"before":"48f5dfbcde061c03187911b42a2708ed01e622f5","after":"47972c15481777bc2a063191261f9b0dd571f530","ref":"refs/heads/main","pushedAt":"2023-06-26T13:40:30.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"ayush-agarwal-0502","name":"Ayush Agarwal ","path":"/ayush-agarwal-0502","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/86561124?s=80&v=4"},"commit":{"message":"Update README.md","shortMessageHtmlLink":"Update README.md"}},{"before":"d3391a83828f7ea520e4a657a091481364cde041","after":"48f5dfbcde061c03187911b42a2708ed01e622f5","ref":"refs/heads/main","pushedAt":"2023-06-26T13:27:34.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"ayush-agarwal-0502","name":"Ayush Agarwal ","path":"/ayush-agarwal-0502","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/86561124?s=80&v=4"},"commit":{"message":"Update README.md","shortMessageHtmlLink":"Update README.md"}},{"before":"63003b2c16ab049a0f7caf79b42b5832dd23fdb7","after":"d3391a83828f7ea520e4a657a091481364cde041","ref":"refs/heads/main","pushedAt":"2023-06-25T16:38:08.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"ayush-agarwal-0502","name":"Ayush Agarwal ","path":"/ayush-agarwal-0502","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/86561124?s=80&v=4"},"commit":{"message":"Add files via upload","shortMessageHtmlLink":"Add files via upload"}},{"before":null,"after":"63003b2c16ab049a0f7caf79b42b5832dd23fdb7","ref":"refs/heads/main","pushedAt":"2023-06-25T16:37:27.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"ayush-agarwal-0502","name":"Ayush Agarwal ","path":"/ayush-agarwal-0502","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/86561124?s=80&v=4"},"commit":{"message":"Initial commit","shortMessageHtmlLink":"Initial commit"}}],"hasNextPage":false,"hasPreviousPage":false,"activityType":"all","actor":null,"timePeriod":"all","sort":"DESC","perPage":30,"cursor":"djE6ks8AAAADSR6qkAA","startCursor":null,"endCursor":null}},"title":"Activity · ayush-agarwal-0502/Digital-Schmitt-Trigger-Controller-System-Verilog"}