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The new operation contains\r\ncomplex-number-specific attributes for correct lowering to LLVM IR.\r\n\r\n~I'll add LLVM IR lowering in later PRs as this PR is already large\r\nenough.~ This PR also includes LLVM IR lowering support. It introduces\r\ntwo new operations `cir.complex.real` and `cir.complex.imag` to aid for\r\nLLVM IR lowering. These two new operations extract the real and\r\nimaginary part of a complex value, which is useful during lowering\r\nprepare, during which phase the complex arithmetic operations are broken\r\ndown to a series of scalar arithmetic operations on the real and\r\nimaginary parts of the complex operands.","shortMessageHtmlLink":"[CIR] Add support for binary arithmetic operations on complex numbers (<a class=\"issue-link js-issue-link\" data-error-text=\"Failed to load title\" data-id=\"2403197697\" data-permission-text=\"Title is private\" data-url=\"https://github.com/llvm/clangir/issues/730\" data-hovercard-type=\"pull_request\" data-hovercard-url=\"/llvm/clangir/pull/730/hovercard\" href=\"https://github.com/llvm/clangir/pull/730\">…</a>"}},{"before":"a944884b3cd928e0d49f0ff06245844d4e34e5c5","after":"dc9f39d2a3c440cba75a9c1198d37657722200b4","ref":"refs/heads/main","pushedAt":"2024-07-17T19:35:10.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"bcardosolopes","name":"Bruno Cardoso Lopes","path":"/bcardosolopes","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/7115212?s=80&v=4"},"commit":{"message":"[CIR] Add support and enable MLIR's mem2reg for flat CIR (#659)\n\nThis is PR enables generic MLIR's mem2reg pass for the flat CIR code. \r\nI submit this draft PR if someone wants to play with mem2reg right now\r\nand to define the next incremental steps if necessary.\r\n\r\nBriefly, what's important:\r\n1) I used llvm dialect implementation for the inspiration\r\n2) I did not implement interfaces for some of the operations, e.g. for\r\n`cir.get_member`, since looks like mem2reg doesn't handle them - it's\r\nmore about SROA pass.\r\n3) simple tests are added \r\n4) mem2reg is disabled by default, so one need to use it explicitly,\r\nwith the `-fclangir-mem2reg` option\r\n5) There are a couple bugs fixed in the code . The most important is\r\ntablegen for `BranchOp` that assumed same sized operands for branches\r\n(it was extremely hard to detect!).\r\n\r\nNote, that this `mem2reg` implementation work with flat CIR only. First\r\nof all, the MLIR's mem2reg knows how to propagate (and remove) memory\r\nslots only when we can build a graph of blocks (e.g. dom tree is a bread\r\nand butter of mem2reg). Also, given that phi nodes are represents as\r\nblocks with arguments in MLIR, there is no chance to transfer control\r\nflow and `call` a block from another region (and pass some values as\r\nwell).\r\n\r\nThe last one is important and has some relation to `canonicalizer` - may\r\nbe you remember I mentioned this problem once somewhere, when\r\nconditional branch verification fails on target block arguments number\r\nand branch operands number mismatch.\r\n\r\nfinally, short example to play with:\r\n``` \r\nint return_42() {\r\n    int y = 42;\r\n    return y;  \r\n}\r\n```\r\nFirst, without mem2reg enabled `clang tmp.c -fclangir -emit-llvm -S -o\r\n-` :\r\n```\r\ndefine dso_local i32 @return_42() #0 !dbg !3 {\r\n  %1 = alloca i32, i64 1, align 4, !dbg !7\r\n  %2 = alloca i32, i64 1, align 4, !dbg !8\r\n  store i32 42, ptr %2, align 4, !dbg !8\r\n  %3 = load i32, ptr %2, align 4, !dbg !9\r\n  store i32 %3, ptr %1, align 4, !dbg !10\r\n  %4 = load i32, ptr %1, align 4, !dbg !10\r\n  ret i32 %4, !dbg !10\r\n}\r\n\r\n```\r\nand with mem2reg enabled `clang tmp.c -fclangir -fclangir-mem2reg\r\n-emit-llvm -S -o -`:\r\n```\r\ndefine dso_local i32 @return_42() #0 !dbg !3 {\r\n  ret i32 42, !dbg !7\r\n}\r\n```\r\n\r\n\r\nSo. What do you think? Which steps do you expect me to perform? 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This PR temporarily public the\r\nsymbol `createLowerModule` to reuse the logic of preparing a\r\n`LowerModule`, making it easier for future refactor (making\r\n`TargetLoweringInfo` available for most stages in CIR Lowering).","shortMessageHtmlLink":"[CIR][ABI][NFC] Make <code>createLowerModule</code> public (<a class=\"issue-link js-issue-link\" data-error-text=\"Failed to load title\" data-id=\"2405863688\" data-permission-text=\"Title is private\" data-url=\"https://github.com/llvm/clangir/issues/734\" data-hovercard-type=\"pull_request\" data-hovercard-url=\"/llvm/clangir/pull/734/hovercard\" href=\"https://github.com/llvm/clangir/pull/734\">#734</a>)"}},{"before":"96b06285a76f0c3d39d8392fc631af6ec4c671a2","after":"fa1e9b5844dc95c8cceefe657cd06cca0ccabb74","ref":"refs/heads/main","pushedAt":"2024-07-12T18:17:42.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"bcardosolopes","name":"Bruno Cardoso Lopes","path":"/bcardosolopes","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/7115212?s=80&v=4"},"commit":{"message":"[CIR][ABI][NFC] AppleARM64 CXXABI handling in TargetLowering library (#733)\n\nIn [this\r\ncommit](https://github.com/llvm/clangir/commit/e5d840b72c1bdb3276094960e9746e413c6f4456),\r\nminimal support for Darwin aarch64 triples was added. But\r\nTargetLoweringInfo was not updated correspondingly.\r\n\r\nThis could lead to a failure of the test `driver.c` with\r\nCallConvLowering pass enabled (or `LowerModule` used in some other\r\nways).\r\n\r\nThis PR fixes the inconsistency and adds an extra missing feature flag\r\nfor it.","shortMessageHtmlLink":"[CIR][ABI][NFC] AppleARM64 CXXABI handling in TargetLowering library (<a class=\"issue-link js-issue-link\" data-error-text=\"Failed to load title\" data-id=\"2405623315\" data-permission-text=\"Title is private\" data-url=\"https://github.com/llvm/clangir/issues/733\" data-hovercard-type=\"pull_request\" data-hovercard-url=\"/llvm/clangir/pull/733/hovercard\" href=\"https://github.com/llvm/clangir/pull/733\">#…</a>"}},{"before":"42a4292c4d73bc6195c88ee6d59529374288cf0c","after":"96b06285a76f0c3d39d8392fc631af6ec4c671a2","ref":"refs/heads/main","pushedAt":"2024-07-12T18:12:51.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"bcardosolopes","name":"Bruno Cardoso Lopes","path":"/bcardosolopes","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/7115212?s=80&v=4"},"commit":{"message":"[CIR][IR] Fix parsing of dsolocal in cir.func (#732)\n\nas title. document will be in another PR as it seems to be a different\r\nupstream branch","shortMessageHtmlLink":"[CIR][IR] Fix parsing of dsolocal in cir.func (<a class=\"issue-link js-issue-link\" data-error-text=\"Failed to load title\" data-id=\"2404380748\" data-permission-text=\"Title is private\" data-url=\"https://github.com/llvm/clangir/issues/732\" data-hovercard-type=\"pull_request\" data-hovercard-url=\"/llvm/clangir/pull/732/hovercard\" href=\"https://github.com/llvm/clangir/pull/732\">#732</a>)"}},{"before":"965a3bc003b856c37e8fefc1116ea6a261ec54d7","after":"42a4292c4d73bc6195c88ee6d59529374288cf0c","ref":"refs/heads/main","pushedAt":"2024-07-12T00:59:21.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"bcardosolopes","name":"Bruno Cardoso Lopes","path":"/bcardosolopes","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/7115212?s=80&v=4"},"commit":{"message":"[CIR][NFCI] cir.try: improve docs and be more flexible on the region","shortMessageHtmlLink":"[CIR][NFCI] cir.try: improve docs and be more flexible on the region"}},{"before":"c1e7b871a393738f2d08ad7dc0e64b68354bf425","after":"965a3bc003b856c37e8fefc1116ea6a261ec54d7","ref":"refs/heads/main","pushedAt":"2024-07-12T00:44:21.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"bcardosolopes","name":"Bruno Cardoso Lopes","path":"/bcardosolopes","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/7115212?s=80&v=4"},"commit":{"message":"[CIR][Lowering] Exceptions: Add support for flattening cir.try\n\nFor now only handle the cir.try part, cir.catch is coming next. Using flat cir\nfor tests make this easy to incrementally build.","shortMessageHtmlLink":"[CIR][Lowering] Exceptions: Add support for flattening cir.try"}},{"before":"dd9353b3a76b8d393c45b6338549a34c9e63cbf7","after":"c1e7b871a393738f2d08ad7dc0e64b68354bf425","ref":"refs/heads/main","pushedAt":"2024-07-11T21:53:40.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"bcardosolopes","name":"Bruno Cardoso Lopes","path":"/bcardosolopes","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/7115212?s=80&v=4"},"commit":{"message":"[CIR][Fix] FP builtins should lower directly to LLVM builtins (#670)\n\nLLVM lowering for the following operations is introduced in #616 and\r\n#651: `cos`, `exp`, `exp2`, `log`, `log10`, `log2`, `sin`, `sqrt`,\r\n`fmod`, and `pow`. However, they are not lowered to their corresponding\r\nLLVM intrinsics; instead they are transformed to libc calls during\r\nlowering prepare. This does not match the upstream behavior.\r\n\r\nThis PR tries to correct this mistake. It makes all CIR FP intrinsic ops\r\nlower to their corresponding LLVM intrinsics (`fmod` is a special case\r\nand it is lowered to the `frem` LLVM instruction).","shortMessageHtmlLink":"[CIR][Fix] FP builtins should lower directly to LLVM builtins (<a class=\"issue-link js-issue-link\" data-error-text=\"Failed to load title\" data-id=\"2341702750\" data-permission-text=\"Title is private\" data-url=\"https://github.com/llvm/clangir/issues/670\" data-hovercard-type=\"pull_request\" data-hovercard-url=\"/llvm/clangir/pull/670/hovercard\" href=\"https://github.com/llvm/clangir/pull/670\">#670</a>)"}},{"before":"c8492103f1f15e89e101be3ef87a9421eff3842e","after":"dd9353b3a76b8d393c45b6338549a34c9e63cbf7","ref":"refs/heads/main","pushedAt":"2024-07-10T20:31:03.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"bcardosolopes","name":"Bruno Cardoso Lopes","path":"/bcardosolopes","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/7115212?s=80&v=4"},"commit":{"message":"[CIR][ThroughMLIR] Lower CIR IV load with SCF IV move operation (#729)\n\nPreviously, when lowering induction variable in forOp, we removed the IV\r\nload and replaced the users with SCF.IV.\r\n\r\nThe CIR IV users might still CIR operations during lowering forOp. It\r\ncaused the issue that CIR operation contained SCF.IV as operand which is\r\nMLIR integer type instead CIR type.\r\n\r\nThis comment lower\r\n    CIR load IV_ADDR\r\nwith\r\n    ARITH addi SCF.IV, 0\r\n\r\nSo SCF.IV can be propagated by OpAdaptor when lowering individual IV\r\nusers. This simplifies the lowering and fixes the issue. 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However, the\r\nsignedness is then restored (still capsuled by a CIR attribute) and\r\ndropped again in the translation into LLVM IR.","shortMessageHtmlLink":"[CIR][Dialect] Emit OpenCL kernel metadata (<a class=\"issue-link js-issue-link\" data-error-text=\"Failed to load title\" data-id=\"2379685550\" data-permission-text=\"Title is private\" data-url=\"https://github.com/llvm/clangir/issues/705\" data-hovercard-type=\"pull_request\" data-hovercard-url=\"/llvm/clangir/pull/705/hovercard\" href=\"https://github.com/llvm/clangir/pull/705\">#705</a>)"}},{"before":"80e1a10002fce76d0880ef15ff8f481dcad626c1","after":"7c4d03a87adee529988ada0dde4cc396f20a9fd0","ref":"refs/heads/main","pushedAt":"2024-07-10T18:35:49.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"bcardosolopes","name":"Bruno Cardoso Lopes","path":"/bcardosolopes","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/7115212?s=80&v=4"},"commit":{"message":"[CIR][NFC] Fix bug in MLIR lowering of cir.call (#728)\n\nThis PR fixes the bug described as in\r\nhttps://github.com/llvm/clangir/issues/727#issuecomment-2219515908. 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It would work with a literal `0` or `1`, but\r\nnot with a literal `true` or `false`.\r\n\r\nThe bug was in `isCstWeak` in CIRGenAtomic.cpp, which was only looking\r\nfor an integral constant. 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