diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 96000ec11fa3f..242033bc6a5e6 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -11678,9 +11678,9 @@ static bool isTargetShuffleEquivalent(MVT VT, ArrayRef<int> Mask,
   return true;
 }
 
-// Attempt to create a shuffle mask from a VSELECT condition mask.
+// Attempt to create a shuffle mask from a VSELECT/BLENDV condition mask.
 static bool createShuffleMaskFromVSELECT(SmallVectorImpl<int> &Mask,
-                                         SDValue Cond) {
+                                         SDValue Cond, bool IsBLENDV = false) {
   EVT CondVT = Cond.getValueType();
   unsigned EltSizeInBits = CondVT.getScalarSizeInBits();
   unsigned NumElts = CondVT.getVectorNumElements();
@@ -11698,7 +11698,8 @@ static bool createShuffleMaskFromVSELECT(SmallVectorImpl<int> &Mask,
     // Arbitrarily choose from the 2nd operand if the select condition element
     // is undef.
     // TODO: Can we do better by matching patterns such as even/odd?
-    if (UndefElts[i] || EltBits[i].isZero())
+    if (UndefElts[i] || (!IsBLENDV && EltBits[i].isZero()) ||
+        (IsBLENDV && EltBits[i].isNonNegative()))
       Mask[i] += NumElts;
   }
 
@@ -43905,9 +43906,10 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
 
   // Convert vselects with constant condition into shuffles.
   if (CondConstantVector && DCI.isBeforeLegalizeOps() &&
-      N->getOpcode() == ISD::VSELECT) {
+      (N->getOpcode() == ISD::VSELECT || N->getOpcode() == X86ISD::BLENDV)) {
     SmallVector<int, 64> Mask;
-    if (createShuffleMaskFromVSELECT(Mask, Cond))
+    if (createShuffleMaskFromVSELECT(Mask, Cond,
+                                     N->getOpcode() == X86ISD::BLENDV))
       return DAG.getVectorShuffle(VT, DL, LHS, RHS, Mask);
   }
 
diff --git a/llvm/test/CodeGen/X86/avx-select.ll b/llvm/test/CodeGen/X86/avx-select.ll
index 1ed71c327fce0..316b51128c5ab 100644
--- a/llvm/test/CodeGen/X86/avx-select.ll
+++ b/llvm/test/CodeGen/X86/avx-select.ll
@@ -58,26 +58,20 @@ define <4 x i64> @select01(i32 %a, <4 x i64> %b) nounwind {
   ret <4 x i64> %res
 }
 
-; FIXME: If a X86ISD::BLENDV node appears before legalization, constant fold using (mask < 0) instead of like a vselect (mask != 0).
+; If a X86ISD::BLENDV node appears before legalization, constant fold using (mask < 0) instead of like a vselect (mask != 0).
 define void @fold_blendv_mask(<4 x i32> %a0) {
 ; X86-LABEL: fold_blendv_mask:
 ; X86:       # %bb.0: # %entry
-; X86-NEXT:    vmovaps {{.*#+}} xmm0 = [44158,54560,45291,18686]
-; X86-NEXT:    vmovaps {{.*#+}} xmm1 = [4294942349,7802,29242,15858]
-; X86-NEXT:    vblendvps %xmm0, {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm0
-; X86-NEXT:    vmovaps {{.*#+}} xmm1 = [29361,4294951202,4294964216,4294941010]
-; X86-NEXT:    vmovaps %xmm1, (%eax)
-; X86-NEXT:    vmovaps %xmm0, (%eax)
+; X86-NEXT:    vmovaps {{.*#+}} ymm0 = [4294942349,7802,29242,15858,29361,4294951202,4294964216,4294941010]
+; X86-NEXT:    vmovaps %ymm0, (%eax)
+; X86-NEXT:    vzeroupper
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: fold_blendv_mask:
 ; X64:       # %bb.0: # %entry
-; X64-NEXT:    vmovaps {{.*#+}} xmm0 = [44158,54560,45291,18686]
-; X64-NEXT:    vmovaps {{.*#+}} xmm1 = [4294942349,7802,29242,15858]
-; X64-NEXT:    vblendvps %xmm0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
-; X64-NEXT:    vmovaps {{.*#+}} xmm1 = [29361,4294951202,4294964216,4294941010]
-; X64-NEXT:    vmovaps %xmm1, (%rax)
-; X64-NEXT:    vmovaps %xmm0, (%rax)
+; X64-NEXT:    vmovaps {{.*#+}} ymm0 = [4294942349,7802,29242,15858,29361,4294951202,4294964216,4294941010]
+; X64-NEXT:    vmovaps %ymm0, (%rax)
+; X64-NEXT:    vzeroupper
 ; X64-NEXT:    retq
 entry:
   br label %head