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principal.asm
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principal.asm
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#include <P18F4550.INC>
; CONFIG1L
CONFIG PLLDIV = 1 ; PLL Prescaler Selection bits (No prescale (4 MHz oscillator input drives PLL directly))
CONFIG CPUDIV = OSC1_PLL2 ; System Clock Postscaler Selection bits ([Primary Oscillator Src: /1][96 MHz PLL Src: /2])
CONFIG USBDIV = 1 ; USB Clock Selection bit (used in Full-Speed USB mode only; UCFG:FSEN = 1) (USB clock source comes directly from the primary oscillator block with no postscale)
; CONFIG1H
CONFIG FOSC = HS ; Oscillator Selection bits (HS oscillator (HS))
CONFIG FCMEN = OFF ; Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
CONFIG IESO = OFF ; Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)
; CONFIG2L
CONFIG PWRT = OFF ; Power-up Timer Enable bit (PWRT disabled)
CONFIG BOR = SOFT ; Brown-out Reset Enable bits (Brown-out Reset enabled and controlled by software (SBOREN is enabled))
CONFIG BORV = 3 ; Brown-out Reset Voltage bits (Minimum setting 2.05V)
CONFIG VREGEN = OFF ; USB Voltage Regulator Enable bit (USB voltage regulator disabled)
; CONFIG2H
CONFIG WDT = OFF ; Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))
CONFIG WDTPS = 32768 ; Watchdog Timer Postscale Select bits (1:32768)
; CONFIG3H
CONFIG CCP2MX = OFF ; CCP2 MUX bit (CCP2 input/output is multiplexed with RB3)
CONFIG PBADEN = OFF ; PORTB A/D Enable bit (PORTB<4:0> pins are configured as digital I/O on Reset)
CONFIG LPT1OSC = OFF ; Low-Power Timer 1 Oscillator Enable bit (Timer1 configured for higher power operation)
CONFIG MCLRE = ON ; MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled)
; CONFIG4L
CONFIG STVREN = OFF ; Stack Full/Underflow Reset Enable bit (Stack full/underflow will not cause Reset)
CONFIG LVP = OFF ; Single-Supply ICSP Enable bit (Single-Supply ICSP disabled)
CONFIG ICPRT = OFF ; Dedicated In-Circuit Debug/Programming Port (ICPORT) Enable bit (ICPORT disabled)
CONFIG XINST = OFF ; Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))
; CONFIG5L
CONFIG CP0 = OFF ; Code Protection bit (Block 0 (000800-001FFFh) is not code-protected)
CONFIG CP1 = OFF ; Code Protection bit (Block 1 (002000-003FFFh) is not code-protected)
CONFIG CP2 = OFF ; Code Protection bit (Block 2 (004000-005FFFh) is not code-protected)
CONFIG CP3 = OFF ; Code Protection bit (Block 3 (006000-007FFFh) is not code-protected)
; CONFIG5H
CONFIG CPB = OFF ; Boot Block Code Protection bit (Boot block (000000-0007FFh) is not code-protected)
CONFIG CPD = OFF ; Data EEPROM Code Protection bit (Data EEPROM is not code-protected)
; CONFIG6L
CONFIG WRT0 = OFF ; Write Protection bit (Block 0 (000800-001FFFh) is not write-protected)
CONFIG WRT1 = OFF ; Write Protection bit (Block 1 (002000-003FFFh) is not write-protected)
CONFIG WRT2 = OFF ; Write Protection bit (Block 2 (004000-005FFFh) is not write-protected)
CONFIG WRT3 = OFF ; Write Protection bit (Block 3 (006000-007FFFh) is not write-protected)
; CONFIG6H
CONFIG WRTC = OFF ; Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) are not write-protected)
CONFIG WRTB = OFF ; Boot Block Write Protection bit (Boot block (000000-0007FFh) is not write-protected)
CONFIG WRTD = OFF ; Data EEPROM Write Protection bit (Data EEPROM is not write-protected)
; CONFIG7L
CONFIG EBTR0 = OFF ; Table Read Protection bit (Block 0 (000800-001FFFh) is not protected from table reads executed in other blocks)
CONFIG EBTR1 = OFF ; Table Read Protection bit (Block 1 (002000-003FFFh) is not protected from table reads executed in other blocks)
CONFIG EBTR2 = OFF ; Table Read Protection bit (Block 2 (004000-005FFFh) is not protected from table reads executed in other blocks)
CONFIG EBTR3 = OFF ; Table Read Protection bit (Block 3 (006000-007FFFh) is not protected from table reads executed in other blocks)
; CONFIG7H
CONFIG EBTRB = OFF ; Boot Block Table Read Protection bit (Boot block (000000-0007FFh) is not protected from table reads executed in other blocks)
CBLOCK 0x00
variableAux;Defenicion de la variable
variableCuenta
ENDC
ORG 0X000; Damos la dirección de inicio para la memoria de programa
GOTO MAIN ; Usamos el alias para designar que será el MAIN
ORG 0X008 ; Usamos el vector para poner la rutina de servicio a la interrupcion de alta prioridad
GOTO SER_ALTA_PRIOR ; Ponemos el alias respectivos
ORG 0X018; Realizamos lo mismo para poder dar la direccion de la segunda funcion de servicio a interrupcion
GOTO SER_BAJA_PRIOR; Ponemos el alias
ORG 0X20; Damos la direccion de memoria para la rutina principal
MAIN:
CLRF TRISD; Ponemos como salida a todo el puerto B
SETF TRISB; Usamos la senticia SETF para ahorrar ciclos de instr.
START: ; Ponemos la etiqueta como alias de la funcion inferior
MOVF PORTB, W ; Movemos el valor del file PORTB y lo guardamos en el registro W
MOVWF variableAux; Llevamos el valor del registro de trabako hacia el operando "variableAux"
COMF variableAux, F; Sacamos el complemento de la variable y lo guardamos en el mismo operando
MOVF variableAux, W; Llevamos el valor de variableAux hacia el registro de trabajo W
MOVWF LATD; Llevamos el valor de W havia el puerto D
GOTO START; Retornamos al posicion de memoria con el alias START
ORG 0X0A0; Damos una direccion en la memoria de programa para la rutina de servicio a la interrupcion de alta prior
SER_ALTA_PRIOR: ; Damos el alias de la rutina de servicio
RETFIE ;Usamos el retorno de interrupciones
ORG 0X0B0; Hacemos lo mismo para la funcion de servicio de la interrupcion de baja prior
SER_BAJA_PRIOR: ; Ponemos el alias
RETFIE ; Ponemos el retorno de interrupciones
END ;Finalizamos la rutina principal