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When I tried to generate the "Cpu0GenCodeEmitter.inc" with tablegen(LLVM Cpu0GenCodeEmitter.inc -gen-emitter), It failed with the following message.
lib/Target/Cpu0/Cpu0InstrInfo.td:1037:5: error: No operand named addr in record JSUB
def JSUB : JumpLink<0x3b, "jsub">;
^
note: Dumping record for previous error:
much more messages ...
Finally, I found the "FJ" in "Cpu0InstrFormats.td" has defined "bits<24> addr;" field,
however, the "class JumpLink" adopt the "$target" as follows.
let isCall=1, hasDelaySlot=1 in {
//@JumpLink {
class JumpLink<bits<8> op, string instr_asm>:
- FJ<op, (outs), (ins calltarget:$target, variable_ops),
- !strconcat(instr_asm, "\t$target"), [(Cpu0JmpLink imm:$target)],
IIBranch> {
//#if CH >= CH10_1 2
let DecoderMethod = "DecodeJumpTarget";
class FJ<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern,
InstrItinClass itin>: Cpu0Inst<outs, ins, asmstr, pattern, itin, FrmJ>
{
bits<24> addr;
let Opcode = op;
let Inst{23-0} = addr;
}
After replacing the "$target" to "$addr", tblgen build successfully.
hi, @Jonathan2251:
When I tried to generate the "Cpu0GenCodeEmitter.inc" with
tablegen(LLVM Cpu0GenCodeEmitter.inc -gen-emitter)
, It failed with the following message.Finally, I found the "FJ" in "Cpu0InstrFormats.td" has defined "bits<24> addr;" field,
however, the "class JumpLink" adopt the "$target" as follows.
After replacing the "$target" to "$addr", tblgen build successfully.
Have you found this issue, or it's just a regression from the llvm project's evolution?
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