Logic synthesis is a process by which an abstract specification of desired circuit behavior, typically at register transfer level (RTL), is turned into a design implementation in terms of logic gates, typically by a computer program called a synthesis tool.
Common examples of this process include synthesis of designs specified in hardware description languages, including VHDL and Verilog.
Some synthesis tools generate bitstreams for programmable logic devices such as PALs or FPGAs, while others target the creation of ASICs. Logic synthesis is one aspect of electronic design automation.
This course will cover various aspects of logic optimization including 1.Representations for Boolean Functions 2. Two-Level Logic Minimization 3. Multi-Level Logic Minimization 4. Timing Optimization 5. Technology Mapping 6. Synthesis for Finite State Machines 7. Low Power Design 8. Automatic Test Pattern Generation 9. Synthesis for hardware security