Some Question about to use HLS #8
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Hello @dianerbaba, Thank you for the feedback and your interest in the project. I will consider updating the codegen user guide to clarify the HLS steps and provide more examples. To get a better understanding on how to use Vivado HLS to create HDL code or IP cores from C++ function definitions (including the solvers generated by ORTiS solver codegen tool), I recommend looking at the Vivado HLS user guide (UG902). Here is a link to the guide on Xilinx website, for version 2019.2: https://docs.xilinx.com/v/u/2019.2-English/ug902-vivado-high-level-synthesis The UG902 guide provides examples and detailed information for HLS'ing top-level functions in general. This guide can also help you to understand how to HLS the solver functions into IP cores for use in Vivado. In general, Vivado HLS converts your C or C++ function code definitions into IP cores, or HDL code definitions, which you can deploy into FPGA designs you write within regular (RTL) Vivado. To use the HLS tool, you first write a non-template function that will serve as your top-level definition for the IP core you wish to create for FPGA deployment, such as a simulation solver core for instance. The arguments and return value of the function act as input/output signal ports of the resultant IP core. For the solver functions generated by the ORTiS solver codegen tool, these solver functions are wrapped by a top-level function since the solver functions are generally defined as function templates which cannot be top-level in Vivado HLS. Then, you test the functionality of your top-level function using a C or C++ testbench. The testbench will usually provide inputs (stimulus) to the function and record the outputs (response) to either memory or file. It may even compare the outputs to "golden data" to confirm the function is working correctly. For the solvers generated by ORTiS solver codegen tool, the testbench effectively runs a circuit simulation with the solver function, calling it within a loop where each iteration corresponds to a single simulation time step. After providing HLS directives (with pragmas inline with C/C++ code or in HLS project settings) which specify the resource usage, timing, scheduling (latency and II), and I/O protocols of the resultant IP core that will be synthesized by the HLS tool (see codegen tool user guide and Vivado HLS guide), you run high level synthesis on the top-level function. This synthesis step will generate VHDL and Verilog definitions of the IP core version of the top-level function, following the HLS directives. Synthesis may also create any Vivado TCL scripts for instancing any internal IP cores the top-level may require (such as a floating-point math unit for instance if using floating point). At this stage, you could copy the generated HDL code and scripts over to a regular RTL Vivado project to use the IP core in a FPGA design. However, depending on complexity of the IP core, you may want to perform other tests or export the IP core into a package that can be used in Vivado's IP integrator or block design approach. The next step you can take is optional but can be useful: running C(++)/RTL cosimulation. This step reruns your C/C++ testbench, but instead of calling the C/C++ function definition of your top-level, it instead calls the generated HDL code of your top-level which is run in the Xilinx RTL simulator in step with the C/C++ testbench. In this step, Vivado HLS runs the testbench twice, once in pure C/C++ and a second time with C/C++ plus RTL code. With cosimulation, you can verify the synthesized HDL code gives comparable or matching results to the C/C++ version of the top-level. Cosimulation can be slow, depending on top-level complexity, so consider that when testing the HDL code behavior. The last (and also optional but recommended) step is to export the RTL HDL code of the top-level for IP integration within Vivado. This step produces a Vivado RTL project around the HDL code of the top-level function and with the project generates an IP core package that can be used in block designs of other Vivado projects. This step can also perform out-of-context low-level synthesis and place-and-route (implementation) to get more exact indications of the resource usage and timing of the IP core than what is estimated during the HLS report. That is the summary of using HLS to create FPGA IP cores from C/C++ functions. Let me know if you have any specific questions. |
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Thanks a lot for developing such a great tool. But I have the following problem, when I try to try to use the HLS tool, I call the generated C++ template directly inside the toplevel function, but what to do next. it is not very clear in the user guide v 0.9, can you provide a simple example of how to generate a bin file from HLS to inside Vivado. I think it would be very helpful for all those who are interested in this project.
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