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index.json
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index.json
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{
"type":"SoC",
"name":"FE310",
"series":["FE310"],
"peripheral": ["ADC","UART","I2C","SPI","PWM"],
"package":["LQFP144","LQFP100","LQFP64","LQFP48","QFN36"],
"manufacturer": {
"vendor":"SiFive",
"homepage":"https://www.sifive.com/"
},
"url":"http://www.SoC.xin/FE310",
"repo":"https://github.com/SoCXin/FE310",
"version":"1.0.0",
"UID": {
"bits": 96,
"base": "0x1FFFF7E8",
"addr": 536868840
},
"Core": {
"num": 1,
"architecture":"RISC-V",
"Freq":[64,72]
},
"FE310": {
"SRAM":20000,
"Flash":64000,
"package":"QFN20",
"peripheral": ["ADC","TIM","PWM"],
"GPIO":18,
"price":6.8
},
"UART": {
"mark": ["UART1","UART2"],
"BIT":[5,6,7,8,9],
"ISO7816":true,
"LIN":true,
"BPS": [48,3000000]
},
"ADC": {
"num": 1,
"channel": 8,
"resolution": 12,
"rate": 1024
},
"TIM": {
"mark": ["TIM1","TIM3","TIM14"],
"TIM1":[16,4,0],
"TIM3":[16,3,0],
"TIM14":[16,1,0],
"systick": 24,
"WWDG": true,
"IWDG": true
},
"CLK": {
"HSE": [1000,16000],
"HSI": [16000],
"LSI": [32],
"PLL": [16000,16000],
"DIV": [1,128],
"accuracy": 0.02
},
"PWR": {
"VDD": [2000,3600],
"PVD": [1820,1810],
"IDD": [2.21,14.31],
"Imax": 120
},
"EMC": {
"EFT": 2000,
"ESD": 4000
},
"upload": {
"ISP": true,
"IAP": true,
"SWD": true,
"speed": 115200
}
}