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diff.txt
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diff --git a/hardware/generator_z/cb/cb.vp b/hardware/generator_z/cb/cb.vp
index b47cf6d..b6b0c53 100644
--- a/hardware/generator_z/cb/cb.vp
+++ b/hardware/generator_z/cb/cb.vp
@@ -1,12 +1,15 @@
//; use POSIX;
+//; my $num_poles = parameter(Name=>'num_poles', val=> 8, doc=>'Number of poles on a NEM relay');
//; my $width = parameter(Name=>'width', val=> 16, doc=>'Bus width for CB');
//; my $num_tracks = parameter(Name=>'num_tracks', val=> 10, doc=>'num of tracks for CB');
-//; my $feedthrough_outputs = parameter(Name=>'feedthrough_outputs', val=> "1111101111", doc=>'binary vector for specifying tracks that are muxed. MSB corresponds to track 0 eg: 1011 means tracks 0, 2, 3 are muxed to produce output for PE. Length in bits = num_tracks.');
-//; my $has_constant = parameter(Name=>'has_constant', val=> 1, doc=>'set to 1 if the CB has a register to supply a constant ');
+//; my $feedthrough_outputs = parameter(Name=>'feedthrough_outputs', val=> "1111111111", doc=>'binary vector for specifying tracks that are muxed. MSB corresponds to track 0 eg: 1011 means tracks 0, 2, 3 are muxed to produce output for PE. Length in bits = num_tracks.');
+//; my $has_constant = parameter(Name=>'has_constant', val=> 0, doc=>'set to 1 if the CB has a register to supply a constant ');
//; my $default_value = parameter(Name=>'default_value', val=> 0, doc=>'set default cb output value on reset. has_constant should be 1 to enable this feature');
//; my @feedthrough = split('',$feedthrough_outputs);
+//; my $mux_drive = parameter(Name=>'mux_drive', val=> 0, doc=>'drive strength of mux buffer');
+//; my $module_name = parameter(Name=>'module_name', val=>"cb_unq1", doc=>'Name of the module');
-module `mname` (
+module `$module_name` (
clk, reset,
//; for(my $i=0; $i<$num_tracks; $i++) {
//; if ($feedthrough[($i%$num_tracks)]==1) {
@@ -34,9 +37,9 @@ read_data
/* verilator lint_off UNUSED */
input [31:0] config_addr;
/* verilator lint_on UNUSED */
- wire ___genesis_wire_`${default_value}`_`${width}`_`${num_tracks}`_`${feedthrough_outputs}`_`${has_constant}`;
+ //wire ___genesis_wire_`${default_value}`_`${width}`_`${num_tracks}`_`${feedthrough_outputs}`_`${has_constant}`;
- output reg [`$width-1`:0] out;
+ output [`$width-1`:0] out;
//; for(my $i=0; $i<$num_tracks; $i++) {
//; if ($feedthrough[$i%$num_tracks]==1) {
input [`$width-1`:0] in_`$i`;
@@ -97,23 +100,42 @@ read_data
//;print CBINFO " <default>$reset_val</default>\n";
//;print CBINFO " <mux snk='out'>\n";
//; my $sel=0;
- always @(*) begin
- case (config_cb[`$mux_sel_bit_count - 1`:0])
-//; for(my $i=0; $i<$num_tracks; $i++) {
-//; if ($feedthrough[$i%$num_tracks]==1) {
- `$mux_sel_bit_count`'d`$sel`: out = in_`$i`;
-//; print CBINFO " <src sel='$sel'>in_$i</src>\n";
-//; $sel++;
-//; }
+ wire [`$num_tracks-1`:0] mux_sel;
+
+ cb_unq1_decoder cb_unq1_decoder (
+ .in(config_cb[`$mux_sel_bit_count - 1`:0]),
+ .out(mux_sel)
+ );
+
+ wire [`$width-1`:0] out_bar;
+
+//; my $num_8bit_muxes = $width/$num_poles;
+//; $num_8bit_muxes = ($num_8bit_muxes < 1) ? 1 : $num_8bit_muxes;
+//; my $num_bits_routed_per_mux = ($width > $num_poles) ? $num_poles : $width;
+
+//; for (my $mux_num=0; $mux_num<$num_8bit_muxes; $mux_num=$mux_num+1) {
+//; my $min_bit = $mux_num * $num_bits_routed_per_mux;
+//; my $max_bit = (($mux_num+1)*$num_bits_routed_per_mux)-1;
+
+ nem_ohmux_invd`$mux_drive`_`$num_tracks`i_`$num_bits_routed_per_mux`b `$module_name`_mux_`$min_bit`_`$max_bit` (
+//; for (my $i=0; $i<$num_bits_routed_per_mux; $i=$i+1) {
+//; for(my $j=0; $j<$num_tracks; $j=$j+1){
+ .I`$j`_`$i` (in_`$j`[`$min_bit+$i`]),
//; }
-//; if ($has_constant==1) {
- default: out = config_cb[`$mux_sel_bit_count+$constant_bit_count-1`:`$mux_sel_bit_count`];
-//; $sel++;
-//; } else {
- default: out = `$width`'d0;
-//; }
- endcase
- end
+ .ZN_`$i` (out_bar[`$min_bit+$i`]),
+
+//;}
+//; for (my $i=0; $i<$num_tracks; $i=$i+1) {
+//; if($i==$num_tracks-1){
+ .S`$i` (mux_sel[`$i`])
+//;} else {
+ .S`$i` (mux_sel[`$i`]),
+//;}
+//;}
+ );
+//;}
+ assign out = ~out_bar;
+
endmodule
//;print CBINFO " </mux>\n";
//;close CBINFO;
diff --git a/hardware/generator_z/sb/sb.vp b/hardware/generator_z/sb/sb.vp
index 041082a..36035f3 100644
--- a/hardware/generator_z/sb/sb.vp
+++ b/hardware/generator_z/sb/sb.vp
@@ -1,20 +1,23 @@
//; use POSIX;
+//; my $num_poles = parameter(Name=>'num_poles', val=> 8, doc=>'Number of poles on a NEM relay');
//; my $width = parameter(Name=>'width', val=> 16, doc=>'Bus width for SB');
-//; my $num_tracks = parameter(Name=>'num_tracks', val=> 10, doc=>'number of tracks per side for SB. half of these are inputs for unidirectional SB');
-//; my $sides = parameter(Name=>'sides', val=> 4, doc=>'number of edges for a SB, 4 for a sqarish SB');
-//; my $feedthrough_outputs = parameter(Name=>'feedthrough_outputs', val=> "11000", doc=>'binary vector for feedthrough output config. Affects all sides. MSB corresponds to output 0 eg: 00000010 means output 7 is feedthrough. Length in bits = 0.5*num_tracks.');
-//; my $registered_outputs = parameter(Name=>'registered_outputs', val=> "00110", doc=>'binary vector for registered output config. Affects all sides. MSB corresponds to output 0. Registering feedthrough outputs is ignored.');
+//; my $num_tracks = parameter(Name=>'num_tracks', val=> 5, doc=>'number of tracks per side for SB. half of these are inputs for unidirectional SB');
+//; my $sides = parameter(Name=>'sides', val=> 4, doc=>'number of edges for a SB, 4 for a sqarish SB');
+//; my $feedthrough_outputs = parameter(Name=>'feedthrough_outputs', val=> "00000", doc=>'binary vector for feedthrough output config. Affects all sides. MSB corresponds to output 0 eg: 00000010 means output 7 is feedthrough. Length in bits = 0.5*num_tracks.');
+//; my $registered_outputs = parameter(Name=>'registered_outputs', val=> "11111", doc=>'binary vector for registered output config. Affects all sides. MSB corresponds to output 0. Registering feedthrough outputs is ignored.');
//; my $pe_output_count = parameter(Name=>'pe_output_count', val=> 1, doc=>'Number of PE outputs to be muxed into outgoing driven tracks');
//; my $is_bidi = parameter(Name=>'is_bidi', val=> 0, doc=>'1 if SB pins are bidi. TBD.');
//; my $sb_fs = parameter(Name=>'sb_fs', val=> "10000#10000#10000", doc=>'binary vector for modifying fanin of sb muxes');
+//; my $mux_drive = parameter(Name=>'mux_drive', val=> 1, doc=>'drive strength of mux buffer');
+//; my $module_name = parameter(Name=>'module_name', val=>"sb_unq1", doc=>'Name of the module');
//; my $number_of_outputs = $num_tracks;
//;my $filename = "SB".$self->mname();
//;open(SBINFO, ">$filename") or die "Couldn't open file $filename, $!";
-module `mname` (
-clk, clk_en, reset,
+module `$module_name` (
+clk, clk_en, reset,
//; for(my $i=0; $i<$pe_output_count; $i++) {
pe_output_`$i`,
//; }
@@ -29,7 +32,7 @@ config_addr,
//; # {config_addr_n, ..... , config_addr_1, config_addr_0}
//; #these bits are split into 32 bit chunks and programmed into SB config reg
//; #config addr 0 (LSB) corresponds to the 32 bit chunk configuring driven outputs
-//; #config addresses increase for 32 bit chunks till the register output config bits
+//; #config addresses increase for 32 bit chunks till the register output config bits
config_data,
config_en,
read_data
@@ -53,7 +56,7 @@ read_data
//; for(my $i=0; $i<$pe_output_count; $i++) {
input [`$width-1`:0] pe_output_`$i`;
//; }
-
+
//; for(my $i=0; $i<$sides; $i++) {
//; for(my $j=0; $j<$number_of_outputs; $j++) {
output [`$width-1`:0] out_`$i`_`$j`;
@@ -62,7 +65,7 @@ read_data
//; }
output reg [31:0] read_data;
- wire ___genesis_wire_`${width}`_`${num_tracks}`_`${feedthrough_outputs}`_`${sides}`_`${registered_outputs}`_`${pe_output_count}`_`${is_bidi}`_`${sb_fs}`;
+ //wire ___genesis_wire_`${width}`_`${num_tracks}`_`${feedthrough_outputs}`_`${sides}`_`${registered_outputs}`_`${pe_output_count}`_`${is_bidi}`_`${sb_fs}`;
//; # #################################################
//; # Setup register for SB mux configuration
@@ -80,11 +83,11 @@ read_data
//; my $config_bit_count = $number_of_driven_outputs_per_side * $number_of_config_bits_per_driven_output * $sides;
//; $config_bit_count += ($registered_count * $sides);
-//; if ($config_bit_count>0) {
+//; if ($config_bit_count>0) {
//; my $config_reg_width = int(ceil($config_bit_count/32.0)*32);
reg [`$config_reg_width-1`:0] config_sb;
-
+
//; my $config_addrs_needed = int(ceil($config_bit_count / 32.0));
always @(posedge clk or posedge reset) begin
if (reset==1'b1) begin
@@ -104,7 +107,7 @@ read_data
//; my $nreg_bits = $registered_count * $sides;
//; my $nonreg_bits = $config_bit_count - $nreg_bits;
//; my $mux_default = ($nonreg_bits <= 40) ? 1 : 0;
- //; my $reg_default = 0;
+ //; my $reg_default = 0;
//; {
// SR/NB 12/2017
// Initialize registers to "unregistered" (leading zeroes);
@@ -148,7 +151,7 @@ read_data
//; my $config_reg_width = int(ceil($config_bit_count/32.0)*32);
reg [`$config_reg_width-1`:0] config_ungate;
-
+
//; my $config_ungate_addrs_needed = int(ceil($config_bit_count / 32.0));
always @(posedge clk or posedge reset) begin
if (reset==1'b1) begin
@@ -172,6 +175,9 @@ read_data
//; # ###############################################
//; # Setup all outputs (feedthrough/non-feedthrough)
//; # ###############################################
+//; my $num_8bit_muxes = $width/$num_poles;
+//; $num_8bit_muxes = ($num_8bit_muxes < 1) ? 1 : $num_8bit_muxes;
+//; my $num_bits_routed_per_mux = ($width > $num_poles) ? $num_poles : $width;
//;print SBINFO " <sel_width>$number_of_config_bits_per_driven_output</sel_width>\n";
//; for(my $i=0; $i<$sides; $i++) {
//; my $registered_config_bit_count = 0;
@@ -188,45 +194,106 @@ read_data
//; } else {
//; my $config_bit_r = ($number_of_driven_outputs_per_side * $number_of_config_bits_per_driven_output * $sides) + ($registered_count * $i) + $registered_config_bit_count;
//; my $config_ungate_r = ($registered_count * $i) + $registered_config_bit_count;
- reg [`$width-1`:0] out_`$i`_`$j`_i;
- always @(*) begin
+ wire [`$width-1`:0] out_`$i`_`$j`_i_bar;
//; my $config_bit_l = ($number_of_driven_outputs_per_side * $number_of_config_bits_per_driven_output * $i) + ($number_of_config_bits_per_driven_output * $driven_config_bit_count);
//; $driven_config_bit_count++;
//; my $config_bit_h = $config_bit_l + $number_of_config_bits_per_driven_output-1;
//; # print SBINFO " <mux snk='out_${i}_${j}' bith='$config_bit_h' bitl='$config_bit_l' configr='$config_bit_r'>\n";
//; print SBINFO " <mux snk='out_${i}_${j}' reg_address='@{[floor($config_bit_h/$config_reg_width)]}' ";
//; print SBINFO "bith='$config_bit_h' bitl='$config_bit_l' default='@{[($mux_default==1) ? (2 ** ($config_bit_h-$config_bit_l+1) - 1) : 0]}'>\n";
- case (config_sb[`$config_bit_h`:`$config_bit_l`])
+// wire [`$sides-1`:0] ohsel_side_`$i`_`$j` = 1 << config_sb[`$config_bit_h`:`$config_bit_l`]; // sides is not always the right dimension, but good enough for now
+ wire [`$sides-1`:0] ohsel_side_`$i`_`$j`;
+ sb_decoder_4to1_mux sb_decoder_4to1_mux_`$i`_`$j` (
+ .in(config_sb[`$config_bit_h`:`$config_bit_l`]),
+ .out(ohsel_side_`$i`_`$j`)
+ );
+
+//; for (my $mux_num=0; $mux_num<$num_8bit_muxes; $mux_num=$mux_num+1) {
+//; my $min_bit = $mux_num * $num_bits_routed_per_mux;
+//; my $max_bit = (($mux_num+1)*$num_bits_routed_per_mux)-1;
+ nem_ohmux_invd`$mux_drive`_`$sides`i_`$num_bits_routed_per_mux`b `$module_name`_side_sel_`$i`_`$j`_`$min_bit`_`$max_bit` (
+//; for(my $l=0; $l<$num_bits_routed_per_mux; $l++){
//; my $sel = 0;
-//; for(my $k=0; $k<$sides; $k++) {
+//; my $k = 0;
+//; for($k=0; $k<$sides; $k++) {
//; if ($k == $i) {next;}
- `$number_of_config_bits_per_driven_output`'d`$sel`: out_`$i`_`$j`_i = in_`$k`_`$j`;
+ .I`$sel`_`$l` (in_`$k`_`$j`[`$min_bit+$l`]),
//; print SBINFO " <src sel='$sel'>in_${k}_${j}</src>\n";
//; $sel++;
//; }
-//; for(my $k=0; $k<$pe_output_count; $k++) {
- `$number_of_config_bits_per_driven_output`'d`$sel`: out_`$i`_`$j`_i = pe_output_`$k`;
-//; print SBINFO " <src sel='$sel'>pe_output_${k}</src>\n";
+//; for(my $m=0; $m<$pe_output_count; $m++) {
+ .I`$sel`_`$l` (pe_output_`$m`[`$min_bit+$l`]),
+//; print SBINFO " <src sel='$sel'>pe_output_${m}</src>\n";
//; $sel++;
//; }
//; print SBINFO " </mux>\n";
- default: out_`$i`_`$j`_i = 0;
- endcase
- end
-//;
+ .ZN_`$l` (out_`$i`_`$j`_i_bar[`$min_bit+$l`]),
+
+//; }
+//; my $k = 0;
+//; my $sel = 0;
+//; my $index = 0;
+//; for($k=0; $k<$sides; $k++) {
+//; if ($k == $i) {next;}
+//; $index = $k-1;
+//; $index = ($index < 0) ? 0 : $index;
+ .S`$sel` (ohsel_side_`$i`_`$j`[`$index`]),
+//; $sel++;
+//; }
+//; for(my $m=0; $m<$pe_output_count; $m++) {
+//; if ($m==$pe_output_count-1){
+ .S`$sel` (ohsel_side_`$i`_`$j`[`$k-1+$m`])
+ );
+//; } else {
+ .S`$sel` (ohsel_side_`$i`_`$j`[`$k-1+$m`]),
+//; }
+//; $sel++;
+//; }
+//; }
+
//; if ($registered[$j]==1) {
//; my $bithl_reg = $config_bit_r % $config_reg_width;
-//; print SBINFO " <reg src='out_${i}_${j}' reg_address='@{[floor($config_bit_r/$config_reg_width)]}' ";
+//; print SBINFO " <reg src='out_${i}_${j}' reg_address='@{[floor($config_bit_r/$config_reg_width)]}' ";
//; print SBINFO "bith='$bithl_reg' bitl='$bithl_reg' default='$reg_default' />\n";
- reg [`$width-1`:0] out_`$i`_`$j`_id1;
+ reg [`$width-1`:0] out_`$i`_`$j`_id1_bar;
wire out_`$i`_`$j`_le;
- assign out_`$i`_`$j`_le = clk_en | (config_ungate[`$config_ungate_r`]);
+ assign out_`$i`_`$j`_le = clk_en | (config_ungate[`$config_ungate_r`]);
always @(posedge clk) begin
if (out_`$i`_`$j`_le)
- out_`$i`_`$j`_id1 <= out_`$i`_`$j`_i;
- end
+ out_`$i`_`$j`_id1_bar <= out_`$i`_`$j`_i_bar;
+ end
+
+ wire [`$width-1`:0] out_`$i`_`$j`_id1;
+ assign out_`$i`_`$j`_id1 = ~out_`$i`_`$j`_id1_bar;
//; $registered_config_bit_count++;
- assign out_`$i`_`$j` = config_sb[`$config_bit_r`]?out_`$i`_`$j`_id1:out_`$i`_`$j`_i;
+
+//; for (my $mux_num=0; $mux_num<$num_8bit_muxes; $mux_num=$mux_num+1) {
+//; my $min_bit = $mux_num * $num_bits_routed_per_mux;
+//; my $max_bit = (($mux_num+1)*$num_bits_routed_per_mux)-1;
+
+//; if($mux_num==0) {
+ wire mux_sel_`$config_bit_r`;
+ wire mux_sel_bar_`$config_bit_r`;
+
+ sb_decoder_2to1_mux sb_decoder_2to1_mux_`$config_bit_r` (
+ .in(config_sb[`$config_bit_r`]),
+ .out(mux_sel_`$config_bit_r`),
+ .out_bar(mux_sel_bar_`$config_bit_r`)
+ );
+//; }
+
+ nem_ohmux_invd`$mux_drive`_2i_`$num_bits_routed_per_mux`b `$module_name`_mux_gate_`$i`_`$j`_`$min_bit`_`$max_bit`(
+//; for(my $k=0; $k<$num_bits_routed_per_mux; $k++) {
+ .I0_`$k` (out_`$i`_`$j`_i_bar[`$min_bit+$k`]),
+ .I1_`$k` (out_`$i`_`$j`_id1_bar[`$min_bit+$k`]),
+ .ZN_`$k`(out_`$i`_`$j`[`$min_bit+$k`]),
+
+//; }
+ .S0(mux_sel_bar_`$config_bit_r`),
+ .S1(mux_sel_`$config_bit_r`)
+ );
+
+//; }
//; } else {
assign out_`$i`_`$j` = out_`$i`_`$j`_i;
//; }
@@ -238,7 +305,7 @@ read_data
//; my $count = 0;
always @ (*) begin
- case (config_addr[31:24])
+ case (config_addr[31:24])
//; for (my $j=0; $j<$config_addrs_needed; $j=$j+1) {
8'd`$count`: read_data = config_sb[`($j+1)*32-1`:`$j*32`];
//; $count++;
@@ -260,7 +327,7 @@ read_data
endmodule
//;# generate corresponding testbench
-//;# my $tb = generate_base('tb_sb', 'tb_sb', width => $width, num_tracks => $num_tracks, sides => $sides, feedthrough_outputs => $feedthrough_outputs, registered_outputs => $registered_outputs, pe_output_count => $pe_output_count, is_bidi => $is_bidi, number_of_outputs => $number_of_outputs);
+//;# my $tb = generate_base('tb_sb', 'tb_sb', width => $width, num_tracks => $num_tracks, sides => $sides, feedthrough_outputs => $feedthrough_outputs, registered_outputs => $registered_outputs, pe_output_count => $pe_output_count, is_bidi => $is_bidi, number_of_outputs => $number_of_outputs);
//;# generate corresponding place and route scripts
//;# my $pnr = generate_base('sb_pnr', 'sb_pnr');