Generate reconfigurable hardware

[hansemandse]

The constant matrix-vector multiplication hardware currently produced by the tool is highly efficient, yet it provides no flexibility in terms of changing weights at runtime. It is an interesting design point to consider similar circuits with this functionality available.

We expect the overheads from barrel shifters and control and storage logic to be rather significant, but it may still be possible to achieve higher area efficiency than with a fully exact, rolled-out matrix multiplication unit.

For this implementation to work, the tool needs to be able to encode factors into a format that is understandable by the hardware with minimal overheads. One possible solution for this is a combined (sign, shift amount) format, in which shift amount is a two's complement integer. It is not yet well-established how to handle special cases of $\pm0.0$ and $\pm1.0$ factors in this format.