clb_dump.vcd

$date
	Sun Jun 25 14:24:46 2023
$end
$version
	Icarus Verilog
$end
$timescale
	1s
$end
$scope module clb_test $end
$var wire 1 ! clb_out $end
$var reg 1 " A $end
$var reg 1 # B $end
$var reg 1 $ C $end
$var reg 1 % clk $end
$var reg 1 & reset $end
$var reg 1 ' select $end
$var reg 8 ( variable_logic [7:0] $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
b110011 (
0'
0&
0%
0$
0#
0"
1!
$end
#5
1"
#10
0!
1#
#15
1!
0#
#16
1%
#20
1'
#25