-
Notifications
You must be signed in to change notification settings - Fork 113
/
sk3wldbg_riscv.cpp
258 lines (234 loc) · 11.4 KB
/
sk3wldbg_riscv.cpp
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
/*
Source for Sk3wlDbg IdaPro plugin
Copyright (c) 2022 Chris Eagle
This program is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the Free
Software Foundation; either version 2 of the License, or (at your option)
any later version.
This program is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
this program; if not, write to the Free Software Foundation, Inc., 59 Temple
Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include "sk3wldbg_riscv.h"
static const char *riscv_regclasses[] = {
"General registers",
"Floating point registers",
NULL
};
enum riscvRegClass {
RISCV_GENERAL = 1,
RISCV_FPU = 2
};
static const char* riscv_flags[] = {
"CR0", "CR0", "CR0", "CR0",
"CR1", "CR1", "CR1", "CR1",
"CR2", "CR2", "CR2", "CR2",
"CR3", "CR3", "CR3", "CR3",
"CR4", "CR4", "CR4", "CR4",
"CR5", "CR5", "CR5", "CR5",
"CR6", "CR6", "CR6", "CR6",
"CR7", "CR7", "CR7", "CR7"
};
static const char* riscv_xer_flags[] = {
"SO", "OV", "CA", NULL, NULL,
NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL,
NULL, NULL,
"COUNT", "COUNT", "COUNT", "COUNT", "COUNT"
};
static const char* riscv_fpu_flags[] = {
"FX", "FEX", "VX", "OX",
"UX", "ZX", "XX", "VXSNAN",
"VXISI", "VXIDI", "VXZDZ", "VXIMZ",
"VXVC", "FR", "FI", "FPRF",
"FPRF", "FPRF", "FPRF", "FPRF",
NULL, "VXSOFT", "VXSQRT", "VXCVI",
"VE", "OE", "UE", "ZE",
"XE", "NI", "RN", "RN"
};
static struct register_info_t riscv_regs[] = {
{"GPR0", REGISTER_ADDRESS, RISCV_GENERAL, dt_dword, NULL, 0},
{"GPR1", REGISTER_ADDRESS, RISCV_GENERAL, dt_dword, NULL, 0},
{"GPR2", REGISTER_ADDRESS, RISCV_GENERAL, dt_dword, NULL, 0},
{"GPR3", REGISTER_ADDRESS, RISCV_GENERAL, dt_dword, NULL, 0},
{"GPR4", REGISTER_ADDRESS, RISCV_GENERAL, dt_dword, NULL, 0},
{"GPR5", REGISTER_ADDRESS, RISCV_GENERAL, dt_dword, NULL, 0},
{"GPR6", REGISTER_ADDRESS, RISCV_GENERAL, dt_dword, NULL, 0},
{"GPR7", REGISTER_ADDRESS, RISCV_GENERAL, dt_dword, NULL, 0},
{"GPR8", REGISTER_ADDRESS, RISCV_GENERAL, dt_dword, NULL, 0},
{"GPR9", REGISTER_ADDRESS, RISCV_GENERAL, dt_dword, NULL, 0},
{"GPR10", REGISTER_ADDRESS, RISCV_GENERAL, dt_dword, NULL, 0},
{"GPR11", REGISTER_ADDRESS, RISCV_GENERAL, dt_dword, NULL, 0},
{"GPR12", REGISTER_ADDRESS, RISCV_GENERAL, dt_dword, NULL, 0},
{"GPR13", REGISTER_ADDRESS, RISCV_GENERAL, dt_dword, NULL, 0},
{"GPR14", REGISTER_ADDRESS, RISCV_GENERAL, dt_dword, NULL, 0},
{"GPR15", REGISTER_ADDRESS, RISCV_GENERAL, dt_dword, NULL, 0},
{"GPR16", REGISTER_ADDRESS, RISCV_GENERAL, dt_dword, NULL, 0},
{"GPR17", REGISTER_ADDRESS, RISCV_GENERAL, dt_dword, NULL, 0},
{"GPR18", REGISTER_ADDRESS, RISCV_GENERAL, dt_dword, NULL, 0},
{"GPR19", REGISTER_ADDRESS, RISCV_GENERAL, dt_dword, NULL, 0},
{"GPR20", REGISTER_ADDRESS, RISCV_GENERAL, dt_dword, NULL, 0},
{"GPR21", REGISTER_ADDRESS, RISCV_GENERAL, dt_dword, NULL, 0},
{"GPR22", REGISTER_ADDRESS, RISCV_GENERAL, dt_dword, NULL, 0},
{"GPR23", REGISTER_ADDRESS, RISCV_GENERAL, dt_dword, NULL, 0},
{"GPR24", REGISTER_ADDRESS, RISCV_GENERAL, dt_dword, NULL, 0},
{"GPR25", REGISTER_ADDRESS, RISCV_GENERAL, dt_dword, NULL, 0},
{"GPR26", REGISTER_ADDRESS, RISCV_GENERAL, dt_dword, NULL, 0},
{"GPR27", REGISTER_ADDRESS, RISCV_GENERAL, dt_dword, NULL, 0},
{"GPR28", REGISTER_ADDRESS, RISCV_GENERAL, dt_dword, NULL, 0},
{"GPR29", REGISTER_ADDRESS, RISCV_GENERAL, dt_dword, NULL, 0},
{"GPR30", REGISTER_ADDRESS, RISCV_GENERAL, dt_dword, NULL, 0},
{"GPR31", REGISTER_ADDRESS, RISCV_GENERAL, dt_dword, NULL, 0},
{"FPR0", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR1", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR2", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR3", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR4", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR5", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR6", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR7", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR8", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR9", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR10", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR11", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR12", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR13", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR14", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR15", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR16", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR17", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR18", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR19", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR20", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR21", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR22", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR23", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR24", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR25", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR26", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR27", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR28", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR29", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR30", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR31", 0, RISCV_FPU, dt_double, NULL, 0},
{"LR", REGISTER_ADDRESS, RISCV_GENERAL, dt_dword, NULL, 0},
{"CTR", REGISTER_ADDRESS, RISCV_GENERAL, dt_dword, NULL, 0},
{"PC", REGISTER_ADDRESS | REGISTER_IP, RISCV_GENERAL, dt_dword, NULL, 0},
{"CR", 0, RISCV_GENERAL, dt_dword, riscv_flags, 0xFFFFFFFF},
{"XER", 0, RISCV_GENERAL, dt_dword, riscv_xer_flags, 0xF8000007},
{"FPSCR", 0, RISCV_FPU, dt_dword, riscv_fpu_flags, 0xFFEFFFFF},
};
#define riscv_LR 64
static struct register_info_t riscv_regs64[] = {
{"GPR0", REGISTER_ADDRESS, RISCV_GENERAL, dt_qword, NULL, 0},
{"GPR1", REGISTER_ADDRESS, RISCV_GENERAL, dt_qword, NULL, 0},
{"GPR2", REGISTER_ADDRESS, RISCV_GENERAL, dt_qword, NULL, 0},
{"GPR3", REGISTER_ADDRESS, RISCV_GENERAL, dt_qword, NULL, 0},
{"GPR4", REGISTER_ADDRESS, RISCV_GENERAL, dt_qword, NULL, 0},
{"GPR5", REGISTER_ADDRESS, RISCV_GENERAL, dt_qword, NULL, 0},
{"GPR6", REGISTER_ADDRESS, RISCV_GENERAL, dt_qword, NULL, 0},
{"GPR7", REGISTER_ADDRESS, RISCV_GENERAL, dt_qword, NULL, 0},
{"GPR8", REGISTER_ADDRESS, RISCV_GENERAL, dt_qword, NULL, 0},
{"GPR9", REGISTER_ADDRESS, RISCV_GENERAL, dt_qword, NULL, 0},
{"GPR10", REGISTER_ADDRESS, RISCV_GENERAL, dt_qword, NULL, 0},
{"GPR11", REGISTER_ADDRESS, RISCV_GENERAL, dt_qword, NULL, 0},
{"GPR12", REGISTER_ADDRESS, RISCV_GENERAL, dt_qword, NULL, 0},
{"GPR13", REGISTER_ADDRESS, RISCV_GENERAL, dt_qword, NULL, 0},
{"GPR14", REGISTER_ADDRESS, RISCV_GENERAL, dt_qword, NULL, 0},
{"GPR15", REGISTER_ADDRESS, RISCV_GENERAL, dt_qword, NULL, 0},
{"GPR16", REGISTER_ADDRESS, RISCV_GENERAL, dt_qword, NULL, 0},
{"GPR17", REGISTER_ADDRESS, RISCV_GENERAL, dt_qword, NULL, 0},
{"GPR18", REGISTER_ADDRESS, RISCV_GENERAL, dt_qword, NULL, 0},
{"GPR19", REGISTER_ADDRESS, RISCV_GENERAL, dt_qword, NULL, 0},
{"GPR20", REGISTER_ADDRESS, RISCV_GENERAL, dt_qword, NULL, 0},
{"GPR21", REGISTER_ADDRESS, RISCV_GENERAL, dt_qword, NULL, 0},
{"GPR22", REGISTER_ADDRESS, RISCV_GENERAL, dt_qword, NULL, 0},
{"GPR23", REGISTER_ADDRESS, RISCV_GENERAL, dt_qword, NULL, 0},
{"GPR24", REGISTER_ADDRESS, RISCV_GENERAL, dt_qword, NULL, 0},
{"GPR25", REGISTER_ADDRESS, RISCV_GENERAL, dt_qword, NULL, 0},
{"GPR26", REGISTER_ADDRESS, RISCV_GENERAL, dt_qword, NULL, 0},
{"GPR27", REGISTER_ADDRESS, RISCV_GENERAL, dt_qword, NULL, 0},
{"GPR28", REGISTER_ADDRESS, RISCV_GENERAL, dt_qword, NULL, 0},
{"GPR29", REGISTER_ADDRESS, RISCV_GENERAL, dt_qword, NULL, 0},
{"GPR30", REGISTER_ADDRESS, RISCV_GENERAL, dt_qword, NULL, 0},
{"GPR31", REGISTER_ADDRESS, RISCV_GENERAL, dt_qword, NULL, 0},
{"FPR0", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR1", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR2", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR3", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR4", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR5", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR6", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR7", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR8", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR9", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR10", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR11", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR12", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR13", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR14", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR15", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR16", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR17", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR18", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR19", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR20", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR21", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR22", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR23", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR24", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR25", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR26", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR27", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR28", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR29", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR30", 0, RISCV_FPU, dt_double, NULL, 0},
{"FPR31", 0, RISCV_FPU, dt_double, NULL, 0},
{"LR", REGISTER_ADDRESS, RISCV_GENERAL, dt_qword, NULL, 0},
{"CTR", REGISTER_ADDRESS, RISCV_GENERAL, dt_qword, NULL, 0},
{"PC", REGISTER_ADDRESS | REGISTER_IP, RISCV_GENERAL, dt_qword, NULL, 0},
{"CR", 0, RISCV_GENERAL, dt_dword, riscv_flags, 0xFFF03FFF},
{"XER", 0, RISCV_GENERAL, dt_dword, riscv_xer_flags, 0xF8000007},
{"FPSCR", 0, RISCV_FPU, dt_dword, riscv_fpu_flags, 0xFFEFFFFF},
};
#define RISCV64_LR 64
sk3wldbg_riscv::sk3wldbg_riscv() : sk3wldbg("riscv", UC_ARCH_RISCV, UC_MODE_32) {
//reset any overridden function pointers and setup register name fields
if (debug_mode & UC_MODE_BIG_ENDIAN) {
processor = "riscv";
}
regclasses = riscv_regclasses;
default_regclasses = RISCV_GENERAL; ///< Mask of default printed register classes
registers = riscv_regs; ///< Array of registers. Use registers() to access it
nregs = qnumber(riscv_regs); ///< Number of registers
// reg_map = riscv_reg_map;
bpt_bytes = NULL; ///< Array of bytes for a breakpoint instruction
bpt_size = 0; ///< Size of this array
}
bool sk3wldbg_riscv::save_ret_addr(uint64_t retaddr) {
uc_reg_write(uc, reg_map[RISCV64_LR], &retaddr);
return true;
}
sk3wldbg_riscv64::sk3wldbg_riscv64() : sk3wldbg("riscv", UC_ARCH_RISCV, UC_MODE_64) {
//reset any overridden function pointers and setup register name fields
if (debug_mode & UC_MODE_BIG_ENDIAN) {
processor = "riscv";
}
regclasses = riscv_regclasses;
default_regclasses = RISCV_GENERAL; ///< Mask of default printed register classes
registers = riscv_regs64; ///< Array of registers. Use registers() to access it
nregs = qnumber(riscv_regs64); ///< Number of registers
// reg_map = riscv64_reg_map;
bpt_bytes = NULL; ///< Array of bytes for a breakpoint instruction
bpt_size = 0; ///< Size of this array
}
bool sk3wldbg_riscv64::save_ret_addr(uint64_t retaddr) {
uc_reg_write(uc, reg_map[RISCV64_LR], &retaddr);
return true;
}