BLTS doesn't raise trap correctly

[darbaria]

The RISC-V ISA mandates that if the target address is not 4-byte aligned then the exception must be raised. The check on byte alignment is on the target address, not the target offset. The RTL is raising the trap if the target offset is not 4-byte aligned. Hence, the trap check for BLTS Instructions fails.

For this assertion, we are checking that the axiomise_trap signal currently mapped to CORE.rvfi_trap is raised correctly but it doesn't.

For reference, the spec we have used is the 2019 version of the base ISA. The exact specification lines are recorded here for easy reference.

"The conditional branch instructions will generate an instruction-address-misaligned exception if the target address is not aligned to a four-byte boundary and the branch condition evaluates to true. If the branch condition evaluates to false, the instruction-address-misaligned exception will not be raised."

[darbaria]

BLTS_TRAP.vcd.gz