JALR for misaligned addresses doesn't raise trap

[darbaria]

Page 21 of the RISCV-ISA 2019 version states that "The JAL and JALR instructions will generate an instruction-address-misaligned exception if the target address is not aligned to a four-byte boundary."

This is not implemented correctly in the design. The trap should be raised if the lower two bits are non-zero for the target address that is obtained by summing up the PC and the sign-extended offset.

  //-- This is what the design is doing

as_ISA_JALR_design_raises_TRAP_but_incorrectly:
`ap (`CORE.FETCH_Instr_indirect_jump_a5 && `CORE.FETCH_Instr_indirect_jump_full_target_a5[1] |-> `CORE.FETCH_Instr_non_aborting_isa_trap_a5);