MULH Instruction not working properly

[shivanishah269]

According to RISCV ISA definition of MULH Instruction,
MULH performs an XLEN-bit×XLEN-bit of signedxsigned multiplication and places the upper XLEN bits in the destination register.

According to my observation, data flow of rs1 and rs2 content is as follows, Design signal(FETCH_Instr_mul_in1/2_a5) --> pcpi_rs1/2 --> mul.rs1/2 --> mul.rs1/2_q. Similar to MUL, here also the multiplication is executed based on contents of rs1_q and rs2_q which are uninitialized values.

Apart from this, I also observe that mul.rs1 and mul.rs2 are unsigned values at cycle 22 instead of signed values according to the definition. Also, the updated result in axiomise_regfile[10] (which is wrong) is the lower half of mul.rd instead of the upper half.

Check the screenshot attached.