Division by 0 case not implemented correctly in the design

[shivanishah269]

Page 44 of the RISC-V ISA mandates "The quotient of division by zero has all bits set, and the remainder of division by zero equals the dividend."

Our checker fails showing that the updates did not happen in cycle 38 to the register 28 in response to a prior divu instruction detected in cycle 37. The attached snapshot shows the entire behaviour from before reset.