REMU Instruction not working correctly

[shivanishah269]

Page 44 of RISC-V ISA mandates "REMU: Divides x[rs1] by x[rs2] rounding towards 0, treating the values as un-signed numbers and writes the remainder to x[rd]"

Our checker fails showing that the updates did not happen in cycle 38 to the register 18 in response to a prior remu instruction detected in cycle 37. x[14] is divided by x[5] and rd is 18. We expect x[18] to be 1 as x[14] is 13 and x[5] is 2, but it isn't.