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Z80_IO.c
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Z80_IO.c
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//http://z80-heaven.wikidot.com/instructions-set
//https://gist.github.com/seanjensengrey/f971c20d05d4d0efc0781f2f3c0353da
//#warning CFR Z80HW per modifiche a gestione flag... 2022
#include <stdio.h>
#include <ctype.h>
#include <stdlib.h>
#include <string.h>
//#include <graph.h>
//#include <dos.h>
//#include <malloc.h>
//#include <memory.h>
//#include <fcntl.h>
//#include <io.h>
#include <xc.h>
#include "Adafruit_ST77xx.h"
#include "Adafruit_ST7735.h"
#include "adafruit_gfx.h"
#include "Z80_PIC.h"
#pragma check_stack(off)
// #pragma check_pointer( off )
#pragma intrinsic( _enable, _disable )
#undef Z80_EXTENDED
BYTE fExit=0;
BYTE debug=0;
#define UNIMPLEMENTED_MEMORY_VALUE 0xFF
#ifdef ZX80
#define RAM_START 0x4000
#define RAM_SIZE 1024
#define ROM_SIZE 4096 // 4K, ZX80; 8K, ZX81
#elif ZX81
#define RAM_START 0x4000
#define RAM_SIZE 1024
#define ROM_SIZE 8192 // 4K, ZX80; 8K, ZX81
#elif SKYNET
#define RAM_START 0x8000
#define RAM_SIZE 2048
#define ROM_SIZE 0x4000
#define ROM_SIZE2 0x4000
#elif NEZ80
#define RAM_START 0x0000
#define RAM_SIZE 2048
#define ROM_START 0x8000
#define ROM_SIZE 0x400
//#define ROM_SIZE2 0x4000
#elif GALAKSIJA
#define RAM_START 0x2800
#define RAM_SIZE (2048*3) // max 3x6116 = 0x1800
#define ROM_START 0x0000
#define ROM_SIZE 0x1000
#define ROM_SIZE2 0x1000
#elif MSX
#define RAM_START 0x8000
#define RAM_SIZE 32768
//#define RAM_START 0xc000
//#define RAM_SIZE 16384 ma DEVE partire dal Top!!
//#define RAM_START 0xf000 // per VELOCIZZAER debug!
//#define RAM_SIZE 4096 // ma DEVE partire dal Top!!
#define RAM_SIZE2 65536
#define RAM_START2 0x0000 // in slot 2, v.sotto
#define ROM_START 0x0000
#define ROM_SIZE 32768
// OCCHIO slot!! v.sotto
#endif
BYTE ram_seg[RAM_SIZE];
#ifdef RAM_SIZE2
BYTE ram_seg2[RAM_SIZE2];
#endif
BYTE rom_seg[ROM_SIZE];
#ifdef ROM_SIZE2
BYTE rom_seg2[ROM_SIZE2];
#endif
#ifdef SKYNET
BYTE i8255RegR[4],i8255RegW[4];
BYTE LCDram[256 /*4*40*/],LCDCGDARAM=0,LCDCGram[64],LCDCGptr=0,LCDfunction,LCDdisplay,
LCDentry=2 /* I/D */,LCDcursor; // emulo LCD text come Z80net
signed char LCDptr=0;
BYTE IOExtPortI[4],IOExtPortO[4];
BYTE IOPortI,IOPortO,ClIRQPort,ClWDPort;
/*Led1Bit equ 7
Led2Bit equ 6
SpeakerBit equ 5
WDEnBit equ 3
ComOutBit2 equ 2
NMIEnBit equ 1
ComOutBit equ 0
Puls1Bit equ 7
ComInBit2 equ 5
DipSwitchBit equ 1
ComInBit equ 0*/
BYTE i146818RegR[2],i146818RegW[2],i146818RAM[64];
BYTE i8042RegR[2],i8042RegW[2];
BYTE KBDataI,KBDataO,KBControl,/*KBStatus,*/ KBRAM[32]; // https://wiki.osdev.org/%228042%22_PS/2_Controller
#define KBStatus KBRAM[0] // pare...
BYTE Keyboard[1]={0};
volatile BYTE TIMIRQ,VIDIRQ,KBDIRQ,SERIRQ,RTCIRQ;
#endif
#ifdef NEZ80
BYTE DisplayRAM[8];
BYTE Keyboard[1]={0};
volatile BYTE TIMIRQ;
BYTE sense50Hz;
volatile BYTE MUXcnt;
#endif
#ifdef ZX80
volatile BYTE TIMIRQ,lineCntr;
//http://searle.x10host.com/zx80/zx80.html
BYTE Keyboard[8]={255,255,255,255,255,255,255,255};
/* There are forty ($28) system variables followed by Program area
; These are located at the start of RAM.
;
; +---------+---------+-----------+---+-----------+-----------+-------+-------+
; | | | | | | | | |
; | SYSVARS | Program | Variables |80h| WKG Space | Disp File | Spare | Stack |
; | | | | | | | | |
; +---------+---------+-----------+---+-----------+-----------+-------+-------+
; ^ ^ ^ ^ ^ ^ ^
; $4024 VARS E_LINE D_FILE DF_END SP
; DF_EA
*/
#endif
#ifdef ZX81
volatile BYTE TIMIRQ,NMIGenerator=0;
BYTE Keyboard[8]={255,255,255,255,255,255,255,255};
#endif
#ifdef GALAKSIJA
volatile BYTE TIMIRQ;
BYTE Keyboard[8]={255,255,255,255,255,255,255,255};
BYTE Latch=0;
/* About the latch
; ***************
; A 6-bit register (called "latch" in the original documentation) can be
; accessed on all memory addresses that can be written in binary as
; 0 0 1 0 0 x x x x x 1 1 1 x x x
; (for example 207fh as used in VIDEO_INT)
; The content is write-only. A read from these addresses will return an
; unspecified value.
; Individual bits have the following meaning:
;
; 7 Clamp RAM A7 to one (1 disabled, 0 enabled)
; ---
; 6 Cassette port output bit 0
; ---
; 5 Character generator row bit 3
; ---
; 4 Character generator row bit 2
; ---
; 3 Character generator row bit 1
; ---
; 2 Character generator row bit 0
; Cassette port output bit 1
; ---
; 1 Unused
; ---
; 0 Unused
; Character generator row bits hold the current row of the character being
; drawn to the screen.
; Cassette port is high if both output bits are 1, low if both are 0 and
; zero if one bit is 1 and one is 0.
; Bit 7 forces RAM address line A7 to one. This is required because the top
; bit of the R register never changes (only bottom 7 bits are incremented
; during each opcode).
*/
#endif
#ifdef MSX
volatile BYTE TIMIRQ,VIDIRQ;
volatile WORD TIMEr;
BYTE TMS9918Reg[8],TMS9918RegS,TMS9918Sel,TMS9918WriteStage,TMS9918Buffer;
WORD TMS9918RAMPtr;
BYTE AY38910RegR[16],AY38910RegW[16],AY38910RegSel;
BYTE i8255RegR[4],i8255RegW[4];
BYTE i8251RegR[4],i8251RegW[4];
BYTE i8253RegR[4],i8253RegW[4];
BYTE iPrinter[2];
BYTE VideoRAM[VIDEORAM_SIZE];
BYTE Keyboard[11]={255,255,255,255,255,255,255,255,255,255,255};
#endif
extern volatile BYTE keysFeedPtr;
#define MAX_WATCHDOG 100 // x30mS v. sotto
extern WORD WDCnt;
extern BYTE ColdReset;
BYTE Pipe1;
union /*__attribute__((__packed__))*/ {
SWORD x;
BYTE bb[4];
struct /*__attribute__((__packed__))*/ {
BYTE l;
BYTE h;
// BYTE u; bah no, sposto la pipe quando ci sono le istruzioni lunghe 4...
} b;
} Pipe2;
BYTE GetValue(SWORD t) {
register BYTE i;
#ifdef MSX
switch(t & 0b1100000000000000) {
case 0<<14:
switch(i8255RegW[0] & 0b00000011) { // gestire slot,
case 0:
i=rom_seg[t];
break;
#ifdef RAM_SIZE2
case 2<<4:
if(t>=RAM_START2)
i=ram_seg2[t-RAM_START2];
else
i=UNIMPLEMENTED_MEMORY_VALUE;
break;
#endif
default:
i=UNIMPLEMENTED_MEMORY_VALUE;
break;
}
break;
case 1<<14:
switch(i8255RegW[0] & 0b00001100) { // gestire slot,
case 0:
i=rom_seg[t];
break;
#ifdef RAM_SIZE2
case 2<<4:
if(t>=RAM_START2)
i=ram_seg2[t-RAM_START2];
else
i=UNIMPLEMENTED_MEMORY_VALUE;
break;
#endif
default:
i=UNIMPLEMENTED_MEMORY_VALUE;
break;
}
break;
case 2<<14:
switch(i8255RegW[0] & 0b00110000) { // gestire slot,
case 0<<4:
if(t>=RAM_START)
i=ram_seg[t-RAM_START];
else
i=UNIMPLEMENTED_MEMORY_VALUE;
break;
#ifdef RAM_SIZE2
case 2<<4:
if(t>=RAM_START2)
i=ram_seg2[t-RAM_START2];
else
i=UNIMPLEMENTED_MEMORY_VALUE;
break;
#endif
default:
i=UNIMPLEMENTED_MEMORY_VALUE;
break;
}
break;
case 3<<14:
switch(i8255RegW[0] & 0b11000000) { // gestire slot,
case 0<<6:
if(t>=RAM_START)
i=ram_seg[t-RAM_START];
else
i=UNIMPLEMENTED_MEMORY_VALUE;
break;
#ifdef RAM_SIZE2
case 2<<6:
if(t>=RAM_START2)
i=ram_seg2[t-RAM_START2];
else
i=UNIMPLEMENTED_MEMORY_VALUE;
break;
#endif
default:
i=UNIMPLEMENTED_MEMORY_VALUE;
break;
}
break;
}
#ifdef MSX2
gestire 0xffff per subslot...
#endif
#else
#ifdef NEZ80
if(t >= RAM_START && t < (RAM_START+RAM_SIZE)) {
t-=RAM_START;
i=ram_seg[t];
}
else if(t >= ROM_START && t < (ROM_START+ROM_SIZE)) {
t-=ROM_START;
i=rom_seg[t];
}
#else
#ifdef ZX80
//xché?? t &= 0x7fff;
#endif
#ifdef ZX81
xché?? t &= 0x7fff;
#endif
if(t < ROM_SIZE) { // ZX80, 81, Galaksija
i=rom_seg[t];
}
#ifdef SKYNET
else if((t-0x4000) < ROM_SIZE2) { // SKYNET
i=rom_seg2[t-0x4000];
}
#endif
else if(t >= RAM_START && t < (RAM_START+RAM_SIZE)) {
i=ram_seg[t-RAM_START];
}
#ifdef SKYNET
else if(t==0xe000) { //
// IOPortI = 0b00011100; // dip-switch=0001; v. main
// IOPortI |= 0b00000001; // ComIn
if(PORTDbits.RD2)
IOPortI |= 0x80; // pulsante
else
IOPortI &= ~0x80;
i=IOPortI;
}
else if(t>=0xe002 && t<=0xe003) { // CMOS RAM/RTC (Real Time Clock MC146818)
t &= 0x1;
switch(t) {
case 0:
i=i146818RegR[0];
break;
case 1: // il bit 7 attiva/disattiva NMI boh??
switch(i146818RegW[0] & 0x3f) {
case 0:
i146818RegR[1]=currentTime.sec;
break;
// in mezzo c'è Alarm...
case 2:
i146818RegR[1]=currentTime.min;
break;
case 4:
i146818RegR[1]=currentTime.hour;
break;
// 6 è day of week...
case 7:
i146818RegR[1]=currentDate.mday;
break;
case 8:
i146818RegR[1]=currentDate.mon;
break;
case 9:
i146818RegR[1]=currentDate.year;
break;
case 12:
i146818RegR[1]=i146818RAM[12] = 0; // flag IRQ
break;
default: // qua ci sono i 4 registri e poi la RAM
i146818RegR[1]=i146818RAM[i146818RegW[0] & 0x3f];
break;
}
i=i146818RegR[1];
break;
}
}
else if(t==0xe004) {
ClIRQPort;
}
else if(t==0xe005) {
ClWDPort;
}
#endif
#ifdef GALAKSIJA
else if((t >= 0x2000) && (t <= 0x27ff)) {
// printf("Leggo a %04x: %02x\n",t,CIA1Reg[t & 0xf]);
t &= 0x3f;
if(t<=0x37)
i = Keyboard[t >> 3] & (1 << (t & 0x7)) ? 1 : 0; // i 3 bit bassi pilotano il mux row/lettura, i 3 alti il mux col/scrittura, out è su D0
// in effetti sono 7, ma anche se il sw sforasse si becca cmq latch :)
else
i = Latch; // (in effetti non è leggibile...)
}
#endif
#ifdef MSX
#endif
#endif
#endif
return i;
}
#ifdef SKYNET
#define LCD_BOARD_ADDRESS 0x80
// emulo display LCD testo (4x20, 4x20 o altro) come su scheda Z80:
// all'indirizzo+0 c'è la porta dati (in/out), a +2 i fili C/D, RW e E (E2)
#define IO_BOARD_ADDRESS 0x00
#endif
BYTE InValue(SWORD t) { // OCCHIO pare che siano 16bit anche I/O!
register BYTE i,j;
#ifdef ZX80
// https://electronics.stackexchange.com/questions/51460/how-does-the-zx80-keyboard-avoid-ghosting-and-masking
/*Input from Port FEh (or any other port with A0 zero)
Reading from this port initiates the Vertical Retrace period (and accordingly,
Cassette Output becomes Low), and resets the LINECNTR register to zero,
LINECNTR remains stopped/zero until user terminates retrace - In the ZX81, all
of the above happens only if NMIs are disabled.
Bit Expl.
0-4 Keyboard column bits (0=Pressed)
5 Not used (1)
6 Display Refresh Rate (0=60Hz, 1=50Hz)
7 Cassette input (0=Normal, 1=Pulse)*/
switch(t) { // OCCHIO byte alto! qua è così
/* A8 A9 A10 A11 A12 A13 A14 A15 Keyboard layout
| | | | | | | |
K4 - V G T 5 6 Y H B
K3 - C F R 4 7 U J N
K2 - X D E 3 8 I K M
K1 - Z S W 2 9 O L .
K0 - Shift A Q 1 0 P NL Space
(I'm using K0-K5 to be the inputs to IC 10)
Lines K0,K1,K2,K3,K4 are pulled to 5V by R13,R14,R15,R16,R17*/
/* Port____Line____Bit__0____1____2____3____4__
FEFEh 0 (A8) SHIFT Z X C V
FDFEh 1 (A9) A S D F G
FBFEh 2 (A10) Q W E R T
F7FEh 3 (A11) 1 2 3 4 5
EFFEh 4 (A12) 0 9 8 7 6
DFFEh 5 (A13) P O I U Y
BFFEh 6 (A14) ENTER L K J H
7FFEh 7 (A15) SPC . M N B*/
case 0xFEFE:
i = Keyboard[0];
break;
case 0xFDFE:
i = Keyboard[1];
break;
case 0xFBFE:
i = Keyboard[2];
break;
case 0xF7FE:
i = Keyboard[3];
break;
case 0xEFFE:
i = Keyboard[4];
break;
case 0xDFFE:
i = Keyboard[5];
break;
case 0xBFFE:
i = Keyboard[6];
break;
case 0x7FFE:
i = Keyboard[7];
break;
}
#elif ZX81
switch(t) { // OCCHIO byte alto! qua è così
case 0xFEFE:
i = Keyboard[0];
break;
case 0xFDFE:
i = Keyboard[1];
break;
case 0xFBFE:
i = Keyboard[2];
break;
case 0xF7FE:
i = Keyboard[3];
break;
case 0xEFFE:
i = Keyboard[4];
break;
case 0xDFFE:
i = Keyboard[5];
break;
case 0xBFFE:
i = Keyboard[6];
break;
case 0x7FFE:
i = Keyboard[7];
break;
}
#elif SKYNET
switch(t & 0xff) {
case IO_BOARD_ADDRESS:
case IO_BOARD_ADDRESS+1:
case IO_BOARD_ADDRESS+2:
case IO_BOARD_ADDRESS+3:
i=IOExtPortI[t-IO_BOARD_ADDRESS];
break;
// case 0x0e: // board signature...
//#warning TOGLIERE QUA!
// return 0x68; // LCD
// break;
case LCD_BOARD_ADDRESS:
// per motivi che ora non ricordo, il BIOS indirizza 0..3 mentre la 2°EEprom (casanet) aveva indirizzi doppi o meglio bit 0..1 messi a 2-0
// potrei ricompilare casanet per andare "dritto" 0..3, per ora lascio così (unico problema è conflitto a +6 con la tastiera... amen! tanto scrive solo all'inizio)
// if(i8255RegR[2] & 0b01000000) fare...?
// else i=i8255RegW[0];
if(!(i8255RegR[1] & 1)) // se status...
i8255RegR[0]=0 | (LCDptr & 0x7f); //sempre ready!
else {
if(!LCDCGDARAM) {
i8255RegR[0]=LCDram[LCDptr]; //
if(LCDentry & 2) {
LCDptr++;
if(LCDptr >= 0x7f) // parametrizzare! o forse no, fisso max 127
LCDptr=0;
}
else {
LCDptr--;
if(LCDptr < 0) // parametrizzare!
LCDptr=0x7f; // CONTROLLARE
}
}
else {
i8255RegR[0]=LCDCGram[LCDptr++]; //
LCDCGptr &= 0x3f;
}
}
i=i8255RegR[0];
break;
case LCD_BOARD_ADDRESS+2:
i=i8255RegR[1];
break;
case LCD_BOARD_ADDRESS+4:
// qua c'è la 3° porta del 8255
// il b6 mette a in o out la porta dati A (1=input)
i=i8255RegR[2];
break;
case LCD_BOARD_ADDRESS+5 /* sarebbe 6 ma ovviamente non si può! v. sopra*/:
// 8255 settings
i=i8255RegR[3];
break;
case LCD_BOARD_ADDRESS+6: //
if(i8042RegW[1]==0xAA) { // self test
i8042RegR[0]=0x55;
}
else if(i8042RegW[1]==0xAB) { // diagnostics
i8042RegR[0]=0b00000000;
}
else if(i8042RegW[1]>=0x20 && i8042RegW[1]<0x40) {
i8042RegR[0]=KBRAM[i8042RegW[1] & 0x1f];
}
else if(i8042RegW[1]>=0x60 && i8042RegW[1]<0x80) {
//KBRAM[i8042RegW[1] & 0x1f]
}
else if(i8042RegW[1]==0xC0) {
i8042RegR[0]=KBStatus;
}
else if(i8042RegW[1]==0xD0) {
i8042RegR[0]=KBControl;
}
else if(i8042RegW[1]==0xD1) {
}
else if(i8042RegW[1]==0xD2) {
}
else if(i8042RegW[1]>=0xF0 && i8042RegW[1]<=0xFF) {
}
i=i8042RegR[0];
break;
case LCD_BOARD_ADDRESS+7:
i=i8042RegR[1];
i=0; // non-busy
break;
case LCD_BOARD_ADDRESS+0xe:
i=0x68; // LCD signature
break;
}
#elif NEZ80
/*
LX.382 scheda CPU ram: 0x0000 - 0x03FF eprom: 0x8000 - 0x83FF -
LX.383 interfaccia tastiera esadecimale -
display (out): 0xF0 - 0xF7
tastiera (in): 0xF0
attiva la linea l'NMI dopo l'istruzione successiva.
E' utilizzato per gestire il single-step (out): 0xF8
LX.385 interfaccia cassette - 0xEE - 0xEF
LX.386 espansione di memoria da 8 KBytes
indirizzabile a piacimento a blocchi di 1K in base ai ponticelli ed alle ram inserite (oltre l'indirizzo 0x7FFF oppure se utilizzata insieme all'espansione da 32 KBytes occorre effettuare delle modifiche)
-
LX.392 espansione di memoria da 32 KBytes
indirizzabile a piacimento a blocchi di 16K in base ai ponticelli ed alle ram inserite
-
LX.389 interfaccia stampante - indirizzabile mediante ponticelli sui seguenti indirizzi a scelta:
0x02 - 0x03
0x06 - 0x07
0x0A - 0x0B
0x0E - 0x0F
0x12 - 0x13
0x16 - 0x17
0x1A - 0x1B
0x1E - 0x1F
LX.548 basic da 16 KBytes su eprom eprom: 0x0000 - 0x3FFF -
LX.388 interfaccia video ram: 0xEC00 - 0xEDFF
tastiera: 0xEA
ritraccia video: 0xEB
LX.529 interfaccia video grafica e stampante -
PIO 0 porta A - dati (ram 0): 0x80
PIO 0 porta A - controllo (ram 0): 0x82
PIO 0 porta B - dati (stampante): 0x81
PIO 0 porta B - controllo (stampante): 0x83
PIO 1 porta A - dati (ram 1): 0x84
PIO 1 porta A - controllo (ram 1): 0x86
PIO 1 porta B - dati (tastiera): 0x85
PIO 1 porta B - controllo (tastiera): 0x87
PIO 2 porta A - dati (ram 2): 0x88
PIO 2 porta A - controllo (ram 2): 0x8A
PIO 2 porta B - dati (busy stampante + 40/80 caratteri video): 0x89
PIO 2 porta B - controllo (busy stampante + 40/80 caratteri video): 0x8B
SY6545 registro di indirizzo e di stato: 0x8C
SY6545 registro dati: 0x8D
RAM 3 attributi dei caratteri: 0x8E
beeper: 0x8F
LX.390 interfaccia floppy eprom: 0xF000 - 0xF3FF
registro di comando (o di stato se ci si accede in lettura): 0xD0
registro di traccia: 0xD1
registro di settore: 0xD2
data register (scrive solo se il controller è libero): 0xD3
drive select e side one select: 0xD6
data register (scrive sempre): 0xD7
LX.394-395 programmatore di eprom eprom da programmare: 0x9000 - 0x9FFF
eprom con firmware: 0x8400 - 0x87FF abilitazione programmazione eprom: 0x7F
LX.683 interfaccia hard-disk eprom su scheda floppy LX.390: 0xF000 - 0xF7FF 0xB8 - 0xB9 - 0xBA - 0xBB
*/
switch(t & 0xff) {
case 0xee: // interfaccia cassette
case 0xef:
break;
case 0xf0:
//finire
// j=0;
// Keyboard[0] = 0x15 | 0x80;
// i=(MUXcnt & 8) << 4;
if(MUXcnt & 8) {
i = Keyboard[0];
/*if(i & 128) {
Nop();
Nop();
}*/
}
else {
Keyboard[0] &= 0x7f;
i = Keyboard[0];
}
// i=sense50Hz;
break;
}
#elif GALAKSIJA
#elif MSX
//https://www.msx.org/wiki/I/O_Ports_List
//http://map.grauw.nl/resources/msx_io_ports.php
switch(t & 0xff) {
case 0x80: // 8251, RS232 data
i=ReadUART1();
i8251RegR[0]=i;
break;
case 0x80+1: // RS232 control
i=i8251RegR[1];
break;
case 0x80+2: // RS232 IRQ
i=i8251RegR[2];
break;
case 0x80+3: // n/a
// i=i8251RegR[3];
break;
case 0x84: // counter 0, timer 8253
i=i8253RegR[0];
break;
case 0x84+1: // counter 1
i=i8253RegR[1];
break;
case 0x84+2: // counter 2
i=i8253RegR[2];
break;
case 0x84+3: // 8253 mode
i=i8253RegR[3];
break;
case 0x90: // printer b1=busy read, b0=strobe output
i=iPrinter[1];
break;
case 0x91: // printer data
i=iPrinter[0];
break;
case TMS99xx_BASE:
TMS9918WriteStage=0;
i=TMS9918Buffer;
TMS9918Buffer=VideoRAM[(TMS9918RAMPtr++) & (VIDEORAM_SIZE-1)];
break;
case TMS99xx_BASE+1:
i=TMS9918RegS;
TMS9918RegS &= 0x7f;
TMS9918WriteStage=0;
break;
case TMS99xx_BASE+2: // Palette access port (only v9938/v9958)
TMS9918WriteStage=0;
break;
case TMS99xx_BASE+3: // Indirect register access port (only v9938/v9958)
TMS9918WriteStage=0;
break;
case 0xa0: // sound PSG AY3
i=AY38910RegSel;
break;
case 0xa0+1: // sound write
break;
case 0xa0+2: // sound read
switch(AY38910RegSel) {
case 14: // joystick
if(AY38910RegR[7] & 0b01000000) // if output BUT ONLY INPUT!
i=AY38910RegW[14];
else
i=AY38910RegR[14];
break;
case 15:
if(AY38910RegR[7] & 0b10000000) // if output ALWAYS OUTPUT!!
i=AY38910RegW[15];
else
i=AY38910RegR[15];
break;
default:
i=AY38910RegR[AY38910RegSel];
break;
}
break;
#ifdef MSXTURBO
case 0xa7: // wait
break;
#endif
case 0xa8: // slot-select, 8255
if(i8255RegW[3] & 0b00010000)
i=i8255RegR[0];
else
i=i8255RegW[0];
break;
case 0xa8+1: // keyboard, 8255
if(i8255RegW[3] & 0b00000010) {
i8255RegR[1] = Keyboard[i8255RegW[2] & 0xf /* OCCHIO 11!*/];
i=i8255RegR[1];
}
else
i=i8255RegW[1];
break;
case 0xa8+2: // keyboard scan & cassette ecc, 8255
if(i8255RegW[3] & 0b00000001)
i=i8255RegR[2] & 0xf;
else
i=i8255RegW[2] & 0xf;
if(i8255RegW[3] & 0b00001000)
i |= i8255RegR[2] & 0xf0;
else
i |= i8255RegW[2] & 0xf0;
break;
case 0xa8+3: // 8255
i=i8255RegR[3];
break;
case 0xb4: // calendar clock
break;
case 0xb8: // light pen
break;
case 0xc0: // music
// i=AY38910Reg[t & 0xf];
break;
case 0xc1: // music
// i=AY38910Reg[t & 0xf];
break;
#ifdef MSXTURBO
//This timer is present only on the MSX turbo R
case 0xe6: // timer (S1990) LSB
i=LOBYTE(TIMEr);
break;
case 0xe7: // timer (S1990) MSB
i=HIBYTE(TIMEr);
break;
#endif
case 0xf5: // system control
break;
case 0xf7: // A/V control
break;
}
#endif
#ifdef MSX2
case 0xfc: // Memory Mapper
// (not reliable to read back...)
break;
case 0xfd: // Memory Mapper
break;
case 0xfe: // Memory Mapper
break;
case 0xff: // Memory Mapper
break;
#endif
return i;
}
SWORD GetIntValue(SWORD t) {
register SWORD i;
#ifdef MSX
switch(t & 0b1100000000000000) {
case 0<<14:
switch(i8255RegW[0] & 0b00000011) { // gestire slot,
case 0:
i=MAKEWORD(rom_seg[t],rom_seg[t+1]);
break;
#ifdef RAM_SIZE2
case 2<<4:
if(t>=RAM_START2)
i=MAKEWORD(ram_seg2[t-RAM_START2],ram_seg2[t-RAM_START2+1]);
else
i=MAKEWORD(UNIMPLEMENTED_MEMORY_VALUE,UNIMPLEMENTED_MEMORY_VALUE);
break;
#endif
default:
i=MAKEWORD(UNIMPLEMENTED_MEMORY_VALUE,UNIMPLEMENTED_MEMORY_VALUE);
break;
}
break;
case 1<<14:
switch(i8255RegW[0] & 0b00001100) { // gestire slot,
case 0:
i=MAKEWORD(rom_seg[t],rom_seg[t+1]);
break;
#ifdef RAM_SIZE2
case 2<<4:
if(t>=RAM_START2)
i=MAKEWORD(ram_seg2[t-RAM_START2],ram_seg2[t-RAM_START2+1]);
else
i=MAKEWORD(UNIMPLEMENTED_MEMORY_VALUE,UNIMPLEMENTED_MEMORY_VALUE);
break;
#endif
default:
i=MAKEWORD(UNIMPLEMENTED_MEMORY_VALUE,UNIMPLEMENTED_MEMORY_VALUE);
break;
}
break;
case 2<<14:
switch(i8255RegW[0] & 0b00110000) { // gestire slot,
case 0<<4:
if(t>=RAM_START)
i=MAKEWORD(ram_seg[t-RAM_START],ram_seg[t-RAM_START+1]);
else
i=MAKEWORD(UNIMPLEMENTED_MEMORY_VALUE,UNIMPLEMENTED_MEMORY_VALUE);
break;
#ifdef RAM_SIZE2
case 2<<4:
if(t>=RAM_START2)
i=MAKEWORD(ram_seg2[t-RAM_START2],ram_seg2[t-RAM_START2+1]);
else
i=MAKEWORD(UNIMPLEMENTED_MEMORY_VALUE,UNIMPLEMENTED_MEMORY_VALUE);
break;
#endif
default:
i=MAKEWORD(UNIMPLEMENTED_MEMORY_VALUE,UNIMPLEMENTED_MEMORY_VALUE);
break;
}
break;
case 3<<14:
switch(i8255RegW[0] & 0b11000000) { // gestire slot,
case 0<<6:
if(t>=RAM_START)
i=MAKEWORD(ram_seg[t-RAM_START],ram_seg[t-RAM_START+1]);
else
i=MAKEWORD(UNIMPLEMENTED_MEMORY_VALUE,UNIMPLEMENTED_MEMORY_VALUE);
break;
#ifdef RAM_SIZE2
case 2<<6:
if(t>=RAM_START2)
i=MAKEWORD(ram_seg2[t-RAM_START2],ram_seg2[t-RAM_START2+1]);
else
i=MAKEWORD(UNIMPLEMENTED_MEMORY_VALUE,UNIMPLEMENTED_MEMORY_VALUE);
break;
#endif
default:
i=MAKEWORD(UNIMPLEMENTED_MEMORY_VALUE,UNIMPLEMENTED_MEMORY_VALUE);
break;
}
break;
}
#ifdef MSX2
gestire 0xffff per subslot... ?? qua
#endif
#else
#ifdef NEZ80
if(t >= RAM_START && t < (RAM_START+RAM_SIZE)) {
t-=RAM_START;
i=MAKEWORD(ram_seg[t],ram_seg[t+1]);
}
else if(t >= ROM_START && t < (ROM_START+ROM_SIZE)) {
t-=ROM_START;
i=MAKEWORD(rom_seg[t],rom_seg[t+1]);
}
#else
#ifdef ZX80
// t &= 0x7fff;
// ??
#endif
#ifdef ZX81
t &= 0x7fff;
??
#endif
if(t < ROM_SIZE) { // ZX80, 81, Galaksija,
i=MAKEWORD(rom_seg[t],rom_seg[t+1]);
}
#ifdef SKYNET
else if((t-0x4000) < ROM_SIZE2) { // SKYNET
t-=0x4000;
i=MAKEWORD(rom_seg2[t],rom_seg2[t+1]);
}
#endif
#ifdef GALAKSIJA
else if((t-0x1000) < ROM_SIZE2) { // GALAKSIJA
t-=0x1000;
i=MAKEWORD(rom_seg2[t],rom_seg2[t+1]);
}
#endif
else if(t >= RAM_START && t < (RAM_START+RAM_SIZE)) {
t-=RAM_START;
i=MAKEWORD(ram_seg[t],ram_seg[t+1]);
}
#ifdef GALAKSIJA
// serve??
// if(t<=0x37)
// i = Keyboard[t & 0x7] & (t >> 3) ? 1 : 0; // i 3 bit bassi pilotano il mux lettura, i 3 alti il mux scrittura, out è su D0
// else
// i = Latch; //
#endif
#endif
#endif
return i;
}
BYTE GetPipe(SWORD t) {
#ifdef MSX
switch(t & 0b1100000000000000) {
case 0<<14:
switch(i8255RegW[0] & 0b00000011) { // gestire slot,
case 0:
Pipe1=rom_seg[t++];
Pipe2.b.l=rom_seg[t++];
// Pipe2.b.h=rom_seg[t++];
// Pipe2.b.u=rom_seg[t];
Pipe2.b.h=rom_seg[t];
break;
#ifdef RAM_SIZE2
case 2<<4:
if(t>=RAM_START2) {
t-=RAM_START2;
Pipe1=ram_seg2[t++];
Pipe2.b.l=ram_seg2[t++];
// Pipe2.b.h=ram_seg[t++];
// Pipe2.b.u=ram_seg[t];
Pipe2.b.h=ram_seg2[t];
}
else {
Pipe1=UNIMPLEMENTED_MEMORY_VALUE;
Pipe2.b.l=UNIMPLEMENTED_MEMORY_VALUE;
// Pipe2.b.h=UNIMPLEMENTED_MEMORY_VALUE;
// Pipe2.b.u=UNIMPLEMENTED_MEMORY_VALUE;
Pipe2.b.h=UNIMPLEMENTED_MEMORY_VALUE;
}
break;
#endif
default:
Pipe1=UNIMPLEMENTED_MEMORY_VALUE;
Pipe2.b.l=UNIMPLEMENTED_MEMORY_VALUE;
// Pipe2.b.h=UNIMPLEMENTED_MEMORY_VALUE;
// Pipe2.b.u=UNIMPLEMENTED_MEMORY_VALUE;
Pipe2.b.h=UNIMPLEMENTED_MEMORY_VALUE;
break;
}
break;
case 1<<14:
switch(i8255RegW[0] & 0b00001100) { // gestire slot,
case 0:
Pipe1=rom_seg[t++];