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vivado.log
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#-----------------------------------------------------------
# Vivado v2019.1 (64-bit)
# SW Build 2552052 on Fri May 24 14:47:09 MDT 2019
# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
# Start of session at: Sat Oct 19 01:25:49 2019
# Process ID: 25417
# Current directory: /home/hello/32-Bit-ALU
# Command line: vivado
# Log file: /home/hello/32-Bit-ALU/vivado.log
# Journal file: /home/hello/32-Bit-ALU/vivado.jou
#-----------------------------------------------------------
start_gui
open_project /home/hello/32-Bit-ALU/32-Bit-ALU.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/neeraj/eda/Vivado/2019.1/data/ip'.
update_compile_order -fileset sources_1
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/hello/32-Bit-ALU/32-Bit-ALU.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'testbench' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/hello/32-Bit-ALU/32-Bit-ALU.sim/sim_1/behav/xsim'
xvlog --incr --relax -prj testbench_vlog.prj
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/GenProp.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module GenProp
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/fastAdder32.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fastAdder32
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/fastAdder4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fastAdder4
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/leftShift.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module leftShift
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/multiplier32.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module multiplier32
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/mux2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module mux2
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sim_1/new/testbench.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module testbench
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/hello/32-Bit-ALU/32-Bit-ALU.sim/sim_1/behav/xsim'
xelab -wto c1973a3ab9f641a6860e2e6eb6eedaec --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot testbench_behav xil_defaultlib.testbench xil_defaultlib.glbl -log elaborate.log
Vivado Simulator 2019.1
Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved.
Running: /home/neeraj/eda/Vivado/2019.1/bin/unwrapped/lnx64.o/xelab -wto c1973a3ab9f641a6860e2e6eb6eedaec --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot testbench_behav xil_defaultlib.testbench xil_defaultlib.glbl -log elaborate.log
Using 8 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.mux2
Compiling module xil_defaultlib.leftShift
Compiling module xil_defaultlib.GenProp
Compiling module xil_defaultlib.fastAdder4
Compiling module xil_defaultlib.fastAdder32_default
Compiling module xil_defaultlib.multiplier32_default
Compiling module xil_defaultlib.testbench
Compiling module xil_defaultlib.glbl
Built simulation snapshot testbench_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/home/hello/32-Bit-ALU/32-Bit-ALU.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "testbench_behav -key {Behavioral:sim_1:Functional:testbench} -tclbatch {testbench.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2019.1
Time resolution is 1 ps
source testbench.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
A= 8965523 B= 785122 control= 0 S=3872917958 carry=z overflow=1 lessthan=z equalto=z zero=z
A= 5 B= 5 control= 1 S= 25 carry=z overflow=0 lessthan=z equalto=z zero=z
INFO: [USF-XSim-96] XSim completed. Design snapshot 'testbench_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 6621.848 ; gain = 124.840 ; free physical = 2668 ; free virtual = 13952
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/hello/32-Bit-ALU/32-Bit-ALU.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'testbench' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/hello/32-Bit-ALU/32-Bit-ALU.sim/sim_1/behav/xsim'
xvlog --incr --relax -prj testbench_vlog.prj
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/GenProp.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module GenProp
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/arithmeticRightShift.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module arithmeticRightShift
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/bitwiseAND.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bitwiseAND
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/bitwiseNOT.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bitwiseNOT
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/bitwiseOR.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bitwiseOR
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/bitwiseXOR.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bitwiseXOR
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/equalTo.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module equalTo
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/fastAdder32.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fastAdder32
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/fastAdder4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fastAdder4
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/leftShift.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module leftShift
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/lessThan.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module lessThan
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/logicalLeftShift.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module logicalLeftShift
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/logicalRightShift.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module logicalRightShift
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/main.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module main
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/multiplier32.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module multiplier32
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/mux2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module mux2
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/subtractor32.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module subtractor32
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/twoscomplement.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module twoscomplement
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sim_1/new/testbench.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module testbench
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/hello/32-Bit-ALU/32-Bit-ALU.sim/sim_1/behav/xsim'
xelab -wto c1973a3ab9f641a6860e2e6eb6eedaec --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot testbench_behav xil_defaultlib.testbench xil_defaultlib.glbl -log elaborate.log
Vivado Simulator 2019.1
Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved.
Running: /home/neeraj/eda/Vivado/2019.1/bin/unwrapped/lnx64.o/xelab -wto c1973a3ab9f641a6860e2e6eb6eedaec --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot testbench_behav xil_defaultlib.testbench xil_defaultlib.glbl -log elaborate.log
Using 8 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.GenProp
Compiling module xil_defaultlib.fastAdder4
Compiling module xil_defaultlib.fastAdder32_default
Compiling module xil_defaultlib.mux2
Compiling module xil_defaultlib.leftShift
Compiling module xil_defaultlib.multiplier32_default
Compiling module xil_defaultlib.bitwiseNOT
Compiling module xil_defaultlib.twoscomplement
Compiling module xil_defaultlib.bitwiseAND
Compiling module xil_defaultlib.bitwiseOR
Compiling module xil_defaultlib.subtractor32
Compiling module xil_defaultlib.logicalLeftShift
Compiling module xil_defaultlib.logicalRightShift
Compiling module xil_defaultlib.arithmeticRightShift
Compiling module xil_defaultlib.bitwiseXOR
Compiling module xil_defaultlib.lessThan
Compiling module xil_defaultlib.equalTo
Compiling module xil_defaultlib.main
Compiling module xil_defaultlib.testbench
Compiling module xil_defaultlib.glbl
Built simulation snapshot testbench_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/home/hello/32-Bit-ALU/32-Bit-ALU.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "testbench_behav -key {Behavioral:sim_1:Functional:testbench} -tclbatch {testbench.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2019.1
Time resolution is 1 ps
source testbench.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
A= 8965523 B= 785122 control= 0 S= 9750645 carry=0 overflow=0 lessthan=0 equalto=0 zero=0
A= 5 B= 5 control= 1 S= 25 carry=0 overflow=0 lessthan=0 equalto=0 zero=0
INFO: [USF-XSim-96] XSim completed. Design snapshot 'testbench_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 6638.645 ; gain = 16.797 ; free physical = 2648 ; free virtual = 13927
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/hello/32-Bit-ALU/32-Bit-ALU.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'testbench' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/hello/32-Bit-ALU/32-Bit-ALU.sim/sim_1/behav/xsim'
xvlog --incr --relax -prj testbench_vlog.prj
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/GenProp.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module GenProp
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/arithmeticRightShift.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module arithmeticRightShift
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/bitwiseAND.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bitwiseAND
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/bitwiseNOT.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bitwiseNOT
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/bitwiseOR.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bitwiseOR
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/bitwiseXOR.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bitwiseXOR
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/equalTo.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module equalTo
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/fastAdder32.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fastAdder32
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/fastAdder4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fastAdder4
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/leftShift.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module leftShift
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/lessThan.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module lessThan
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/logicalLeftShift.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module logicalLeftShift
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/logicalRightShift.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module logicalRightShift
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/main.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module main
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/multiplier32.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module multiplier32
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/mux2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module mux2
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/subtractor32.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module subtractor32
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/twoscomplement.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module twoscomplement
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sim_1/new/testbench.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module testbench
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/hello/32-Bit-ALU/32-Bit-ALU.sim/sim_1/behav/xsim'
xelab -wto c1973a3ab9f641a6860e2e6eb6eedaec --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot testbench_behav xil_defaultlib.testbench xil_defaultlib.glbl -log elaborate.log
Vivado Simulator 2019.1
Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved.
Running: /home/neeraj/eda/Vivado/2019.1/bin/unwrapped/lnx64.o/xelab -wto c1973a3ab9f641a6860e2e6eb6eedaec --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot testbench_behav xil_defaultlib.testbench xil_defaultlib.glbl -log elaborate.log
Using 8 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.GenProp
Compiling module xil_defaultlib.fastAdder4
Compiling module xil_defaultlib.fastAdder32_default
Compiling module xil_defaultlib.mux2
Compiling module xil_defaultlib.leftShift
Compiling module xil_defaultlib.multiplier32_default
Compiling module xil_defaultlib.bitwiseNOT
Compiling module xil_defaultlib.twoscomplement
Compiling module xil_defaultlib.bitwiseAND
Compiling module xil_defaultlib.bitwiseOR
Compiling module xil_defaultlib.subtractor32
Compiling module xil_defaultlib.logicalLeftShift
Compiling module xil_defaultlib.logicalRightShift
Compiling module xil_defaultlib.arithmeticRightShift
Compiling module xil_defaultlib.bitwiseXOR
Compiling module xil_defaultlib.lessThan
Compiling module xil_defaultlib.equalTo
Compiling module xil_defaultlib.main
Compiling module xil_defaultlib.testbench
Compiling module xil_defaultlib.glbl
Built simulation snapshot testbench_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/home/hello/32-Bit-ALU/32-Bit-ALU.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "testbench_behav -key {Behavioral:sim_1:Functional:testbench} -tclbatch {testbench.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2019.1
Time resolution is 1 ps
source testbench.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
A= 8965523 B= 785122 control= 1 S=3872917958 carry=0 overflow=1 lessthan=0 equalto=0 zero=0
A= 5 B= 5 control= 1 S= 25 carry=0 overflow=0 lessthan=0 equalto=0 zero=0
INFO: [USF-XSim-96] XSim completed. Design snapshot 'testbench_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 6664.656 ; gain = 26.012 ; free physical = 2673 ; free virtual = 13953
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/hello/32-Bit-ALU/32-Bit-ALU.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'testbench' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/hello/32-Bit-ALU/32-Bit-ALU.sim/sim_1/behav/xsim'
xvlog --incr --relax -prj testbench_vlog.prj
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/GenProp.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module GenProp
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/arithmeticRightShift.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module arithmeticRightShift
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/bitwiseAND.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bitwiseAND
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/bitwiseNOT.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bitwiseNOT
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/bitwiseOR.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bitwiseOR
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/bitwiseXOR.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bitwiseXOR
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/equalTo.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module equalTo
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/fastAdder32.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fastAdder32
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/fastAdder4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fastAdder4
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/leftShift.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module leftShift
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/lessThan.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module lessThan
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/logicalLeftShift.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module logicalLeftShift
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/logicalRightShift.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module logicalRightShift
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/main.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module main
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/multiplier32.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module multiplier32
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/mux2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module mux2
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/subtractor32.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module subtractor32
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/twoscomplement.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module twoscomplement
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sim_1/new/testbench.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module testbench
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/hello/32-Bit-ALU/32-Bit-ALU.sim/sim_1/behav/xsim'
xelab -wto c1973a3ab9f641a6860e2e6eb6eedaec --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot testbench_behav xil_defaultlib.testbench xil_defaultlib.glbl -log elaborate.log
Vivado Simulator 2019.1
Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved.
Running: /home/neeraj/eda/Vivado/2019.1/bin/unwrapped/lnx64.o/xelab -wto c1973a3ab9f641a6860e2e6eb6eedaec --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot testbench_behav xil_defaultlib.testbench xil_defaultlib.glbl -log elaborate.log
Using 8 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.GenProp
Compiling module xil_defaultlib.fastAdder4
Compiling module xil_defaultlib.fastAdder32_default
Compiling module xil_defaultlib.mux2
Compiling module xil_defaultlib.leftShift
Compiling module xil_defaultlib.multiplier32_default
Compiling module xil_defaultlib.bitwiseNOT
Compiling module xil_defaultlib.twoscomplement
Compiling module xil_defaultlib.bitwiseAND
Compiling module xil_defaultlib.bitwiseOR
Compiling module xil_defaultlib.subtractor32
Compiling module xil_defaultlib.logicalLeftShift
Compiling module xil_defaultlib.logicalRightShift
Compiling module xil_defaultlib.arithmeticRightShift
Compiling module xil_defaultlib.bitwiseXOR
Compiling module xil_defaultlib.lessThan
Compiling module xil_defaultlib.equalTo
Compiling module xil_defaultlib.main
Compiling module xil_defaultlib.testbench
Compiling module xil_defaultlib.glbl
Built simulation snapshot testbench_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/home/hello/32-Bit-ALU/32-Bit-ALU.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "testbench_behav -key {Behavioral:sim_1:Functional:testbench} -tclbatch {testbench.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2019.1
Time resolution is 1 ps
source testbench.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
A= 8965523 B= 785122 control= 1 S=3872917958 carry=0 overflow=1 lessthan=0 equalto=0 zero=0
A=4294967291 B= 5 control= 1 S=4294967271 carry=0 overflow=1 lessthan=0 equalto=0 zero=0
INFO: [USF-XSim-96] XSim completed. Design snapshot 'testbench_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 6672.660 ; gain = 8.004 ; free physical = 2653 ; free virtual = 13934
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/hello/32-Bit-ALU/32-Bit-ALU.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'testbench' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/hello/32-Bit-ALU/32-Bit-ALU.sim/sim_1/behav/xsim'
xvlog --incr --relax -prj testbench_vlog.prj
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/GenProp.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module GenProp
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/arithmeticRightShift.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module arithmeticRightShift
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/bitwiseAND.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bitwiseAND
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/bitwiseNOT.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bitwiseNOT
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/bitwiseOR.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bitwiseOR
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/bitwiseXOR.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bitwiseXOR
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/equalTo.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module equalTo
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/fastAdder32.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fastAdder32
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/fastAdder4.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module fastAdder4
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/leftShift.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module leftShift
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/lessThan.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module lessThan
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/logicalLeftShift.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module logicalLeftShift
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/logicalRightShift.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module logicalRightShift
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/main.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module main
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/multiplier32.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module multiplier32
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/mux2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module mux2
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/subtractor32.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module subtractor32
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sources_1/new/twoscomplement.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module twoscomplement
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/hello/32-Bit-ALU/32-Bit-ALU.srcs/sim_1/new/testbench.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module testbench
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/hello/32-Bit-ALU/32-Bit-ALU.sim/sim_1/behav/xsim'
xelab -wto c1973a3ab9f641a6860e2e6eb6eedaec --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot testbench_behav xil_defaultlib.testbench xil_defaultlib.glbl -log elaborate.log
Vivado Simulator 2019.1
Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved.
Running: /home/neeraj/eda/Vivado/2019.1/bin/unwrapped/lnx64.o/xelab -wto c1973a3ab9f641a6860e2e6eb6eedaec --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot testbench_behav xil_defaultlib.testbench xil_defaultlib.glbl -log elaborate.log
Using 8 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.GenProp
Compiling module xil_defaultlib.fastAdder4
Compiling module xil_defaultlib.fastAdder32_default
Compiling module xil_defaultlib.mux2
Compiling module xil_defaultlib.leftShift
Compiling module xil_defaultlib.multiplier32_default
Compiling module xil_defaultlib.bitwiseNOT
Compiling module xil_defaultlib.twoscomplement
Compiling module xil_defaultlib.bitwiseAND
Compiling module xil_defaultlib.bitwiseOR
Compiling module xil_defaultlib.subtractor32
Compiling module xil_defaultlib.logicalLeftShift
Compiling module xil_defaultlib.logicalRightShift
Compiling module xil_defaultlib.arithmeticRightShift
Compiling module xil_defaultlib.bitwiseXOR
Compiling module xil_defaultlib.lessThan
Compiling module xil_defaultlib.equalTo
Compiling module xil_defaultlib.main
Compiling module xil_defaultlib.testbench
Compiling module xil_defaultlib.glbl
Built simulation snapshot testbench_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/home/hello/32-Bit-ALU/32-Bit-ALU.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "testbench_behav -key {Behavioral:sim_1:Functional:testbench} -tclbatch {testbench.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2019.1
Time resolution is 1 ps
source testbench.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
A= 8965523 B= 785122 control= 1 S=3872917958 carry=0 overflow=1 lessthan=0 equalto=0 zero=0
A=4294967291 B=4294967291 control= 1 S= 25 carry=0 overflow=1 lessthan=0 equalto=0 zero=0
INFO: [USF-XSim-96] XSim completed. Design snapshot 'testbench_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 6687.668 ; gain = 15.008 ; free physical = 2632 ; free virtual = 13919
close_sim
INFO: [Simtcl 6-16] Simulation closed
exit
INFO: [Common 17-206] Exiting Vivado at Sat Oct 19 01:46:31 2019...