fix: sys-libs/glibc test failure

glibc tests its ability to detect CPU features by comparing its results
to the /proc/cpuinfo file. The Intel TSX vulnerability called ZombieLoad
2 caused Intel to release a microcode update that disables TSX on
impacted CPUs. Disability TSX has the effect of removing the Hardware
Lock Elision (HLE) CPU flag as well.

The initial microcode update (IPU 2021.1) was updated in IPU 2021.2 to
disable TSX on additional CPUs. glibc has not been updated to account
for this change. This patch adds the new CPU steppings to the list of
steppings that should not support HLE. This issue was encountered on a
Dell Precision 7540 with an Intel Core i9-9980HK CPU.

Refs: https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html
Signed-off-by: Jaremy Hatler <[email protected]>

patches/sys-libs/glibc-2.37/x86-Include-latest-steppings-from-errata-in-HLE-CPU-feature-unset.patch

@@ -0,0 +1,16 @@
+--- a/sysdeps/x86/cpu-features.c	2023-02-01 03:27:45.000000000 +0000
++++ b/sysdeps/x86/cpu-features.c	2024-01-01 16:28:42.530031173 +0000
+@@ -522,8 +522,12 @@
+ 		 the errata was to disable TSX on all client processors on
+ 		 all steppings.  Include 0xc stepping which is an Intel
+ 		 Core i7-8665U, a client mobile processor.  */
++              /* The latest errata documents that IPU 2021.2 microcode
++                 includes the 0xc stepping as well now.  */
+ 	    case 0x9e:
+-	      if (stepping > 0xc)
++              /* The latest errata documents that stepping 0xd should be
++                 included as well now.  */
++	      if (stepping > 0xd)
+ 		break;
+ 	      /* Fall through.  */
+ 	    case 0x4e: