Built By: Joey Maillette
As an engineer with a keen interest in digital systems and logic design, the purpose of this project is to successfully implement combinational logic circuits in VHDL. The primary focus is on the design and simulation of fundamental arithmetic logic units, including a half adder, full adder, and a 4-bit adder.
Rather than solely relying on traditional digital design methodologies, this project utilizes VHDL, a powerful hardware description language, to define the behavior of the mentioned digital circuits. The designs are then synthesized and simulated to verify their correctness and performance.
The design, simulation, and verification of these circuits are facilitated using:
- VHDL
- EDA Playground
- GHDL 0.37 / EPWave