dump.vcd

$date
	Thu Jul 11 11:31:53 2024
$end
$version
	ModelSim Version 2020.4
$end
$timescale
	1ns
$end

$scope module CPU_tb_round $end
$var reg 1 ! clk $end
$var reg 1 " clr $end
$var wire 1 # read $end
$var wire 1 $ write $end
$var wire 1 % memoryIn [7] $end
$var wire 1 & memoryIn [6] $end
$var wire 1 ' memoryIn [5] $end
$var wire 1 ( memoryIn [4] $end
$var wire 1 ) memoryIn [3] $end
$var wire 1 * memoryIn [2] $end
$var wire 1 + memoryIn [1] $end
$var wire 1 , memoryIn [0] $end
$var wire 1 - memoryOut [7] $end
$var wire 1 . memoryOut [6] $end
$var wire 1 / memoryOut [5] $end
$var wire 1 0 memoryOut [4] $end
$var wire 1 1 memoryOut [3] $end
$var wire 1 2 memoryOut [2] $end
$var wire 1 3 memoryOut [1] $end
$var wire 1 4 memoryOut [0] $end
$var wire 1 5 address [3] $end
$var wire 1 6 address [2] $end
$var wire 1 7 address [1] $end
$var wire 1 8 address [0] $end

$scope module CPU_dut $end
$var wire 1 9 clk $end
$var wire 1 : clr $end
$var wire 1 - memoryOut [7] $end
$var wire 1 . memoryOut [6] $end
$var wire 1 / memoryOut [5] $end
$var wire 1 0 memoryOut [4] $end
$var wire 1 1 memoryOut [3] $end
$var wire 1 2 memoryOut [2] $end
$var wire 1 3 memoryOut [1] $end
$var wire 1 4 memoryOut [0] $end
$var wire 1 5 address [3] $end
$var wire 1 6 address [2] $end
$var wire 1 7 address [1] $end
$var wire 1 8 address [0] $end
$var wire 1 % memoryIn [7] $end
$var wire 1 & memoryIn [6] $end
$var wire 1 ' memoryIn [5] $end
$var wire 1 ( memoryIn [4] $end
$var wire 1 ) memoryIn [3] $end
$var wire 1 * memoryIn [2] $end
$var wire 1 + memoryIn [1] $end
$var wire 1 , memoryIn [0] $end
$var wire 1 # read $end
$var wire 1 $ write $end
$var wire 1 ; bus [7] $end
$var wire 1 < bus [6] $end
$var wire 1 = bus [5] $end
$var wire 1 > bus [4] $end
$var wire 1 ? bus [3] $end
$var wire 1 @ bus [2] $end
$var wire 1 A bus [1] $end
$var wire 1 B bus [0] $end
$var wire 1 C alu [7] $end
$var wire 1 D alu [6] $end
$var wire 1 E alu [5] $end
$var wire 1 F alu [4] $end
$var wire 1 G alu [3] $end
$var wire 1 H alu [2] $end
$var wire 1 I alu [1] $end
$var wire 1 J alu [0] $end
$var wire 1 K dr [7] $end
$var wire 1 L dr [6] $end
$var wire 1 M dr [5] $end
$var wire 1 N dr [4] $end
$var wire 1 O dr [3] $end
$var wire 1 P dr [2] $end
$var wire 1 Q dr [1] $end
$var wire 1 R dr [0] $end
$var wire 1 S ac [7] $end
$var wire 1 T ac [6] $end
$var wire 1 U ac [5] $end
$var wire 1 V ac [4] $end
$var wire 1 W ac [3] $end
$var wire 1 X ac [2] $end
$var wire 1 Y ac [1] $end
$var wire 1 Z ac [0] $end
$var wire 1 [ ir [7] $end
$var wire 1 \ ir [6] $end
$var wire 1 ] ir [5] $end
$var wire 1 ^ ir [4] $end
$var wire 1 _ ir [3] $end
$var wire 1 ` ir [2] $end
$var wire 1 a ir [1] $end
$var wire 1 b ir [0] $end
$var wire 1 c ar [3] $end
$var wire 1 d ar [2] $end
$var wire 1 e ar [1] $end
$var wire 1 f ar [0] $end
$var wire 1 g pc [3] $end
$var wire 1 h pc [2] $end
$var wire 1 i pc [1] $end
$var wire 1 j pc [0] $end
$var wire 1 k cout $end
$var wire 1 l loadIR $end
$var wire 1 m incIR $end
$var wire 1 n clrIR $end
$var wire 1 o loadDR $end
$var wire 1 p incDR $end
$var wire 1 q clrDR $end
$var wire 1 r loadPC $end
$var wire 1 s incPC $end
$var wire 1 t clrPC $end
$var wire 1 u loadAR $end
$var wire 1 v incAR $end
$var wire 1 w clrAR $end
$var wire 1 x loadAC $end
$var wire 1 y incAC $end
$var wire 1 z clrAC $end
$var wire 1 { t [7] $end
$var wire 1 | t [6] $end
$var wire 1 } t [5] $end
$var wire 1 ~ t [4] $end
$var wire 1 !! t [3] $end
$var wire 1 "! t [2] $end
$var wire 1 #! t [1] $end
$var wire 1 $! t [0] $end
$var wire 1 %! d [7] $end
$var wire 1 &! d [6] $end
$var wire 1 '! d [5] $end
$var wire 1 (! d [4] $end
$var wire 1 )! d [3] $end
$var wire 1 *! d [2] $end
$var wire 1 +! d [1] $end
$var wire 1 ,! d [0] $end
$var wire 1 -! busSEL [2] $end
$var wire 1 .! busSEL [1] $end
$var wire 1 /! busSEL [0] $end
$var wire 1 0! aluOPCODE [2] $end
$var wire 1 1! aluOPCODE [1] $end
$var wire 1 2! aluOPCODE [0] $end
$var wire 1 3! sc [2] $end
$var wire 1 4! sc [1] $end
$var wire 1 5! sc [0] $end
$var wire 1 6! clrSC $end
$var wire 1 7! busIR $end
$var wire 1 8! busDR $end
$var wire 1 9! busPC $end
$var wire 1 :! busAR $end
$var wire 1 ;! busAC $end
$var wire 1 <! busMem $end
$var wire 1 =! opADD $end
$var wire 1 >! opASHL $end
$var wire 1 ?! opXNOR $end
$var wire 1 @! opDIV2 $end
$var wire 1 A! opLOAD $end
$var wire 1 B! opSTORE $end
$var wire 1 C! opCOMP2S $end
$var wire 1 D! opROUND $end
$var wire 1 E! i $end

$scope module encoder_busSEL $end
$var wire 1 # in [7] $end
$var wire 1 F! in [6] $end
$var wire 1 7! in [5] $end
$var wire 1 ;! in [4] $end
$var wire 1 8! in [3] $end
$var wire 1 9! in [2] $end
$var wire 1 :! in [1] $end
$var wire 1 G! in [0] $end
$var wire 1 -! out [2] $end
$var wire 1 .! out [1] $end
$var wire 1 /! out [0] $end
$upscope $end

$scope module busRoad $end
$var wire 1 H! in0 [7] $end
$var wire 1 I! in0 [6] $end
$var wire 1 J! in0 [5] $end
$var wire 1 K! in0 [4] $end
$var wire 1 L! in0 [3] $end
$var wire 1 M! in0 [2] $end
$var wire 1 N! in0 [1] $end
$var wire 1 O! in0 [0] $end
$var wire 1 P! in1 [7] $end
$var wire 1 Q! in1 [6] $end
$var wire 1 R! in1 [5] $end
$var wire 1 S! in1 [4] $end
$var wire 1 c in1 [3] $end
$var wire 1 d in1 [2] $end
$var wire 1 e in1 [1] $end
$var wire 1 f in1 [0] $end
$var wire 1 T! in2 [7] $end
$var wire 1 U! in2 [6] $end
$var wire 1 V! in2 [5] $end
$var wire 1 W! in2 [4] $end
$var wire 1 g in2 [3] $end
$var wire 1 h in2 [2] $end
$var wire 1 i in2 [1] $end
$var wire 1 j in2 [0] $end
$var wire 1 K in3 [7] $end
$var wire 1 L in3 [6] $end
$var wire 1 M in3 [5] $end
$var wire 1 N in3 [4] $end
$var wire 1 O in3 [3] $end
$var wire 1 P in3 [2] $end
$var wire 1 Q in3 [1] $end
$var wire 1 R in3 [0] $end
$var wire 1 S in4 [7] $end
$var wire 1 T in4 [6] $end
$var wire 1 U in4 [5] $end
$var wire 1 V in4 [4] $end
$var wire 1 W in4 [3] $end
$var wire 1 X in4 [2] $end
$var wire 1 Y in4 [1] $end
$var wire 1 Z in4 [0] $end
$var wire 1 [ in5 [7] $end
$var wire 1 \ in5 [6] $end
$var wire 1 ] in5 [5] $end
$var wire 1 ^ in5 [4] $end
$var wire 1 _ in5 [3] $end
$var wire 1 ` in5 [2] $end
$var wire 1 a in5 [1] $end
$var wire 1 b in5 [0] $end
$var wire 1 X! in6 [7] $end
$var wire 1 Y! in6 [6] $end
$var wire 1 Z! in6 [5] $end
$var wire 1 [! in6 [4] $end
$var wire 1 \! in6 [3] $end
$var wire 1 ]! in6 [2] $end
$var wire 1 ^! in6 [1] $end
$var wire 1 _! in6 [0] $end
$var wire 1 - in7 [7] $end
$var wire 1 . in7 [6] $end
$var wire 1 / in7 [5] $end
$var wire 1 0 in7 [4] $end
$var wire 1 1 in7 [3] $end
$var wire 1 2 in7 [2] $end
$var wire 1 3 in7 [1] $end
$var wire 1 4 in7 [0] $end
$var wire 1 -! sel [2] $end
$var wire 1 .! sel [1] $end
$var wire 1 /! sel [0] $end
$var reg 8 `! out [7:0] $end
$upscope $end

$scope module aluUnit $end
$var wire 1 9 clk $end
$var wire 1 S op1 [7] $end
$var wire 1 T op1 [6] $end
$var wire 1 U op1 [5] $end
$var wire 1 V op1 [4] $end
$var wire 1 W op1 [3] $end
$var wire 1 X op1 [2] $end
$var wire 1 Y op1 [1] $end
$var wire 1 Z op1 [0] $end
$var wire 1 K op2 [7] $end
$var wire 1 L op2 [6] $end
$var wire 1 M op2 [5] $end
$var wire 1 N op2 [4] $end
$var wire 1 O op2 [3] $end
$var wire 1 P op2 [2] $end
$var wire 1 Q op2 [1] $end
$var wire 1 R op2 [0] $end
$var wire 1 0! sel [2] $end
$var wire 1 1! sel [1] $end
$var wire 1 2! sel [0] $end
$var wire 1 C out [7] $end
$var wire 1 D out [6] $end
$var wire 1 E out [5] $end
$var wire 1 F out [4] $end
$var wire 1 G out [3] $end
$var wire 1 H out [2] $end
$var wire 1 I out [1] $end
$var wire 1 J out [0] $end
$var wire 1 k co $end
$var wire 1 a! add [7] $end
$var wire 1 b! add [6] $end
$var wire 1 c! add [5] $end
$var wire 1 d! add [4] $end
$var wire 1 e! add [3] $end
$var wire 1 f! add [2] $end
$var wire 1 g! add [1] $end
$var wire 1 h! add [0] $end
$var wire 1 i! addo $end
$var wire 1 j! ashl [7] $end
$var wire 1 k! ashl [6] $end
$var wire 1 l! ashl [5] $end
$var wire 1 m! ashl [4] $end
$var wire 1 n! ashl [3] $end
$var wire 1 o! ashl [2] $end
$var wire 1 p! ashl [1] $end
$var wire 1 q! ashl [0] $end
$var wire 1 r! ashlo $end
$var wire 1 s! xnr [7] $end
$var wire 1 t! xnr [6] $end
$var wire 1 u! xnr [5] $end
$var wire 1 v! xnr [4] $end
$var wire 1 w! xnr [3] $end
$var wire 1 x! xnr [2] $end
$var wire 1 y! xnr [1] $end
$var wire 1 z! xnr [0] $end
$var wire 1 {! div [7] $end
$var wire 1 |! div [6] $end
$var wire 1 }! div [5] $end
$var wire 1 ~! div [4] $end
$var wire 1 !" div [3] $end
$var wire 1 "" div [2] $end
$var wire 1 #" div [1] $end
$var wire 1 $" div [0] $end
$var wire 1 %" divo $end
$var wire 1 &" comp2s [7] $end
$var wire 1 '" comp2s [6] $end
$var wire 1 (" comp2s [5] $end
$var wire 1 )" comp2s [4] $end
$var wire 1 *" comp2s [3] $end
$var wire 1 +" comp2s [2] $end
$var wire 1 ," comp2s [1] $end
$var wire 1 -" comp2s [0] $end
$var wire 1 ." round [7] $end
$var wire 1 /" round [6] $end
$var wire 1 0" round [5] $end
$var wire 1 1" round [4] $end
$var wire 1 2" round [3] $end
$var wire 1 3" round [2] $end
$var wire 1 4" round [1] $end
$var wire 1 5" round [0] $end

$scope module add_Module $end
$var wire 1 S op1 [7] $end
$var wire 1 T op1 [6] $end
$var wire 1 U op1 [5] $end
$var wire 1 V op1 [4] $end
$var wire 1 W op1 [3] $end
$var wire 1 X op1 [2] $end
$var wire 1 Y op1 [1] $end
$var wire 1 Z op1 [0] $end
$var wire 1 K op2 [7] $end
$var wire 1 L op2 [6] $end
$var wire 1 M op2 [5] $end
$var wire 1 N op2 [4] $end
$var wire 1 O op2 [3] $end
$var wire 1 P op2 [2] $end
$var wire 1 Q op2 [1] $end
$var wire 1 R op2 [0] $end
$var wire 1 a! out [7] $end
$var wire 1 b! out [6] $end
$var wire 1 c! out [5] $end
$var wire 1 d! out [4] $end
$var wire 1 e! out [3] $end
$var wire 1 f! out [2] $end
$var wire 1 g! out [1] $end
$var wire 1 h! out [0] $end
$var wire 1 i! cout $end
$upscope $end

$scope module ashl_Module $end
$var wire 1 K op1 [7] $end
$var wire 1 L op1 [6] $end
$var wire 1 M op1 [5] $end
$var wire 1 N op1 [4] $end
$var wire 1 O op1 [3] $end
$var wire 1 P op1 [2] $end
$var wire 1 Q op1 [1] $end
$var wire 1 R op1 [0] $end
$var wire 1 j! out [7] $end
$var wire 1 k! out [6] $end
$var wire 1 l! out [5] $end
$var wire 1 m! out [4] $end
$var wire 1 n! out [3] $end
$var wire 1 o! out [2] $end
$var wire 1 p! out [1] $end
$var wire 1 q! out [0] $end
$var wire 1 r! cout $end
$upscope $end

$scope module xnor_Module $end
$var wire 1 S op1 [7] $end
$var wire 1 T op1 [6] $end
$var wire 1 U op1 [5] $end
$var wire 1 V op1 [4] $end
$var wire 1 W op1 [3] $end
$var wire 1 X op1 [2] $end
$var wire 1 Y op1 [1] $end
$var wire 1 Z op1 [0] $end
$var wire 1 K op2 [7] $end
$var wire 1 L op2 [6] $end
$var wire 1 M op2 [5] $end
$var wire 1 N op2 [4] $end
$var wire 1 O op2 [3] $end
$var wire 1 P op2 [2] $end
$var wire 1 Q op2 [1] $end
$var wire 1 R op2 [0] $end
$var wire 1 s! out [7] $end
$var wire 1 t! out [6] $end
$var wire 1 u! out [5] $end
$var wire 1 v! out [4] $end
$var wire 1 w! out [3] $end
$var wire 1 x! out [2] $end
$var wire 1 y! out [1] $end
$var wire 1 z! out [0] $end
$upscope $end

$scope module div2_Moudle $end
$var wire 1 K op1 [7] $end
$var wire 1 L op1 [6] $end
$var wire 1 M op1 [5] $end
$var wire 1 N op1 [4] $end
$var wire 1 O op1 [3] $end
$var wire 1 P op1 [2] $end
$var wire 1 Q op1 [1] $end
$var wire 1 R op1 [0] $end
$var wire 1 {! out [7] $end
$var wire 1 |! out [6] $end
$var wire 1 }! out [5] $end
$var wire 1 ~! out [4] $end
$var wire 1 !" out [3] $end
$var wire 1 "" out [2] $end
$var wire 1 #" out [1] $end
$var wire 1 $" out [0] $end
$var wire 1 %" cout $end
$upscope $end

$scope module comp2s_Module $end
$var wire 1 K op1 [7] $end
$var wire 1 L op1 [6] $end
$var wire 1 M op1 [5] $end
$var wire 1 N op1 [4] $end
$var wire 1 O op1 [3] $end
$var wire 1 P op1 [2] $end
$var wire 1 Q op1 [1] $end
$var wire 1 R op1 [0] $end
$var wire 1 &" out [7] $end
$var wire 1 '" out [6] $end
$var wire 1 (" out [5] $end
$var wire 1 )" out [4] $end
$var wire 1 *" out [3] $end
$var wire 1 +" out [2] $end
$var wire 1 ," out [1] $end
$var wire 1 -" out [0] $end
$upscope $end

$scope module roud_Module $end
$var wire 1 K op1 [7] $end
$var wire 1 L op1 [6] $end
$var wire 1 M op1 [5] $end
$var wire 1 N op1 [4] $end
$var wire 1 O op1 [3] $end
$var wire 1 P op1 [2] $end
$var wire 1 Q op1 [1] $end
$var wire 1 R op1 [0] $end
$var reg 8 6" rounded [7:0] $end
$var reg 8 7" temp [7:0] $end
$upscope $end
$upscope $end

$scope module SCounter $end
$var wire 1 9 clk $end
$var wire 1 8" inc $end
$var wire 1 6! clr $end
$var reg 3 9" out [2:0] $end
$upscope $end

$scope module decoder_instruction $end
$var wire 1 \ in [2] $end
$var wire 1 ] in [1] $end
$var wire 1 ^ in [0] $end
$var reg 8 :" out [7:0] $end
$upscope $end

$scope module decoder_sc $end
$var wire 1 3! in [2] $end
$var wire 1 4! in [1] $end
$var wire 1 5! in [0] $end
$var reg 8 ;" out [7:0] $end
$upscope $end

$scope module PC $end
$var wire 1 9 clk $end
$var wire 1 s inc $end
$var wire 1 r load $end
$var wire 1 t clr $end
$var wire 1 ? in [3] $end
$var wire 1 @ in [2] $end
$var wire 1 A in [1] $end
$var wire 1 B in [0] $end
$var reg 4 <" out [3:0] $end
$upscope $end

$scope module AR $end
$var wire 1 9 clk $end
$var wire 1 v inc $end
$var wire 1 u load $end
$var wire 1 w clr $end
$var wire 1 ? in [3] $end
$var wire 1 @ in [2] $end
$var wire 1 A in [1] $end
$var wire 1 B in [0] $end
$var reg 4 =" out [3:0] $end
$upscope $end

$scope module DR $end
$var wire 1 9 clk $end
$var wire 1 p inc $end
$var wire 1 o load $end
$var wire 1 q clr $end
$var wire 1 ; in [7] $end
$var wire 1 < in [6] $end
$var wire 1 = in [5] $end
$var wire 1 > in [4] $end
$var wire 1 ? in [3] $end
$var wire 1 @ in [2] $end
$var wire 1 A in [1] $end
$var wire 1 B in [0] $end
$var reg 8 >" out [7:0] $end
$upscope $end

$scope module AC $end
$var wire 1 9 clk $end
$var wire 1 y inc $end
$var wire 1 x load $end
$var wire 1 z clr $end
$var wire 1 C in [7] $end
$var wire 1 D in [6] $end
$var wire 1 E in [5] $end
$var wire 1 F in [4] $end
$var wire 1 G in [3] $end
$var wire 1 H in [2] $end
$var wire 1 I in [1] $end
$var wire 1 J in [0] $end
$var reg 8 ?" out [7:0] $end
$upscope $end

$scope module IR $end
$var wire 1 9 clk $end
$var wire 1 m inc $end
$var wire 1 l load $end
$var wire 1 n clr $end
$var wire 1 ; in [7] $end
$var wire 1 < in [6] $end
$var wire 1 = in [5] $end
$var wire 1 > in [4] $end
$var wire 1 ? in [3] $end
$var wire 1 @ in [2] $end
$var wire 1 A in [1] $end
$var wire 1 B in [0] $end
$var reg 8 @" out [7:0] $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
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xE
xD
xC
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x[
xf
xe
xd
xc
xj
xi
xh
xg
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0m
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x~!
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0{!
x%"
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0]!
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$end
#5
1!
19
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b1 ;"
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0~
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