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Unleash the power of VLSI design! From logic gates conception through integrated circuit creation to meticulous layout design, sculpt the heart of electronic systems. Dive into a world where every nanometer matters. 🚀🔧 #VLSI #ICDesign
Created AMD-Am2901 chip clone (4-bit ALU) with Cadence Virtuoso from a transistor level, manually creating datapath and generating control via CAD. Skills employed: Cadence Virtuoso, Logic (VLSI) Design, Verilog
• Created a user-friendly to-do list application with features for adding, editing, and deleting tasks. • Utilized local storage to save tasks, ensuring data persistence across browser sessions
This repository is about design and implementation of a time interleaved SAR ADC in Cadence Virtuoso. In this project all the blocks of the ADC is customised and implemented from transistor level itself and no ideal block is used from the libraries of virtuoso.
Cadence Virtuoso Git Integration written in SKILL++, forked from rbennell-gh/cdsgit_lfs, and the cdsgit_lsf is forked from https://github.com/cdsgit/cdsgit
Performance Analysis of a 4-bit Ripple Carry Adder (RCA) formed using Static CMOS, Transmission Gate, NMOS Pass Transistor Logic at gpdk 180nm Technology node.