Designing Single-Cycle Microprocessor without Interlocked Pipeline Stages (MIPS) using Verilog.
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Updated
Jul 5, 2024 - Verilog
Designing Single-Cycle Microprocessor without Interlocked Pipeline Stages (MIPS) using Verilog.
Source code for various Verilog-based projects and assignments
Basic tools, methods and procedures to design combinational and sequential digital circuits and systems. Topics include number systems, Boolean algebra, logic minimization, circuit design, memory elements, and finite state machine design.
EE89H Final Project
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