(Verilog+FPGA EGO1) (140/100) A real car: our project of CS207 2022 Fall: Digital Logic Design, SUSTech. Taught by Prof. James YU @James-Yu.
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Updated
Feb 22, 2023 - Verilog
(Verilog+FPGA EGO1) (140/100) A real car: our project of CS207 2022 Fall: Digital Logic Design, SUSTech. Taught by Prof. James YU @James-Yu.
This is the mirror for gitee in github for project assignment of cs202 / 214 Computer Organization course of Southern University of Science and Technology, which is to manufacture a CPU. 这是南方科技大学CS202/214计算机组成原理课程的大作业——实现一个CPU。
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