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SPI burst read/write #105
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How is it controlled directly? I couldn't spot any SPI register that controls the CS pin? |
I guess SPI hardware output CS low when TX fifo is not empty, and output high CS high after TX fifo is empty for a peroid of time. Currently I did not find detail document about it. |
Couldn't find any documentation either. Quick googling shows that SS might always be low when SPI is enabled: |
The name of pin is misleading. I mean
https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf p504 For my case, frame format is Motorola SPI with SPO=1, SPH=1. I'm pretty sure CS pin will toggle. |
Good job on finding it! Yes, we are definitely missing this functionality. I don't have the bandwidth to work on it in the near future, but if you are up to working on a pull-request, I suggest adding a callback, |
The problem is when |
Yes, it's not trivial. If I understand correctly, the logic behind onCSChange() should more or less reflect the value of the |
My understanding it's not the same with the |
The
onTransmit
has no information about if it's the same transfer (chip select pin keep low). For my case, I need to simulate a SPI slave which has different behavior for different transfer length. The CS pin is controlled directly by hardware, currently I have no idea how to fix it. Any suggestion?rp2040js/src/peripherals/spi.ts
Lines 112 to 119 in cac702d
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