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aal5sar.c
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/**
*
* aal5sar.c
*
* TNETDxxxx Software Support\n
* Copyright (c) 2002 Texas Instruments Incorporated. All Rights Reserved.
*
* version
* 28Feb02 Greg 1.00 Original Version created.\n
* 06Mar02 Greg 1.01 Documentation (Doxygen-style) enhanced
* 06May02 Greg 1.02 AAL2 added
* 06Jun02 Greg 1.03 Multiple API and bug fixes from emulation
* 12Jul02 Greg 1.04 API Update
* 18Sept07 CPH 2.00 CQ11466: Added EFM support
*/
/**
@defgroup CPHAL_Functions CPHAL Functions
These are the CPHAL Functions.
*/
/**
@page CPHAL_Implementation_Details Introduction
The CPHAL API described above is generally applicable to all modules. Any
implementation differences will be described in the following module-specific
appendix sections.
Included for your reference is a diagram showing the internal architecture
of the CPHAL:
@image html SangamSoftware.jpg "HAL Architecture"
@image latex SangamSoftware.jpg "HAL Architecture" height=2.8in
*/
/**
@defgroup AAL5_Functions Additional Functions for AAL5 Implementation
These functions are used only by the AAL5 module.
*/
/*
@defgroup CPMAC_Functions Additional Functions for CPMAC Implementation
No additional functions currently defined.
*/
/**
@page VDMA_Implementation_Details Introduction
The VDMA-VT module facilitates efficient transfer of data (especially voice)
between two devices, as shown in the figure below.
@image html vdma.jpg "VDMA System Block Diagram"
@image latex vdma.jpg "VDMA System Block Diagram" height=1in
The VDMA-VT module supports two modes of operation: mirror mode and credit mode.
Mirror mode is intended for systems in which the remote device does not have a
VDMA-based module. Credit mode is intended for highest performance when VDMA-based
modules exist on both ends of an interface.
For more detailed information on the operation of the VDMA module, please
reference the VDMA Module Guide.
@section vdma_channels VDMA Channels
The VDMA-VT module is a single channel, single transmit queue device. Therefore,
when using the CHANNEL_INFO structure, the correct value for @c Ch is always 0.
Correspondingly, the correct value for the @c Ch parameter in @c ChannelTeardown() is
always 0. Further, when calling @c Send(), the driver should always supply the value
of 0 for both the @c Ch and @c Queue parameters.
For the VDMA-VT, configuring the channel requires the configuration of either 2 FIFO
elements (in credit mode) or 4 FIFO elements (in mirror mode). For credit mode, the
driver must configure just the local Tx and Rx FIFOs. For mirror mode, the driver must
configure the Tx and Rx FIFOs for both the remote and local ends of the interface.
This channel configuration is accomplished through multiple calls to @c ChannelSetup().
Each call configures a single FIFO, according to the parameters in the CHANNEL_INFO
structure. The members of VDMA-VT's CHANNEL_INFO structure are defined below.
- int RemFifoAddr; Address of remote FIFO (mirror mode only). Set to 0 for credit mode.
- int FifoAddr; Address of the local FIFO. If 0, the CPHAL will allocate the FIFO.
- int FifoSize; Size of the FIFO.
- int PollInt; Polling interval for the FIFO.
- int Endianness; Endianness of the FIFO. If 1, big endian. If 0, little endian.
- int RemAddr; Used only in credit mode. This is the base address of the remote
remote VDMA-based device (VDMA-VT or AAL2)
- int RemDevID; Used only in credit mode. Identifies the type of remote VDMA-based device.
0=VDMAVT, 1=AAL2 Ch0, 2=AAL2 Ch1, 3=AAL2 Ch2, 4= AAL2 Ch3.
For the VDMA-VT module, the driver must make all calls to @c ChannelSetup() prior to calling
@c Open(). This is because several of the channel specific parameters may not be changed
while the VDMA-VT module is operational.
@section vdma_params VDMA Parameters
Defined here are the set of parameters for the VDMA-VT module. Default settings for
each parameter should be represented in the device configuration file (options.conf).
During @c Init(), the CPHAL will reference the device configuration file and load all
default settings. The @c Control() interface gives the driver an opportunity to
modify any default settings before the module becomes operational during the @c Open()
call.
@param NoTxIndication If 1, the CPHAL will not call @c SendComplete(). 0 is default.
@param NoRxIndication If 1, the CPHAL will not call @c Receive(). 0 is default.
@param RemoteCPU If 1, the CPHAL will not directly manipulate data in FIFO's, leaving
that task for a remote CPU. 0 is default.
@param RxIntEn If 1, enables Rx interrupts. 0 is default.
@param TxIntEn If 1, enables Tx interrupts. 0 is default.
@param Mirror If 1, enables mirror mode. 0 selects credit mode (default).
@param RxIntCtl Valid only in mirror mode. If 1, interrupts will occur when the Rx FIFO
RdIndex is updated. If 0, interrupts occur when the Rx FIFO WrIndex
is updated.
@param TxIntCtl Valid only in mirror mode. If 1, interrupts will occur when the Rx FIFO
RdIndex is updated. If 0, interrupts occur when the Rx FIFO WrIndex
is updated.
@param RBigEn Remote big endian mode. If 1, remote is big endian.
@param LBigEn Local big endian mode. If 1, local is big endian.
@section vdma_polling Using VDMA-VT without interrupts
If your system configuration does not utilize VDMA interrupts, the ability to process the
Tx and Rx FIFOs is supported. To process the Tx FIFO, call @c CheckTx(). If the CPHAL is
able to process any complete data transmissions, it will call @c SendComplete() as usual.
To process the Rx FIFO, call @c CheckRx(). If the CPHAL has received any data, it will
call @c Receive() to pass the driver the data. Please reference @ref VDMA_Functions for more
information on these interfaces.
@section vdma_details VDMA Implementation Details
The following functions are not defined for use with VDMA: @c Status(), @c Tick(), @c StatsGet(),
and @c StatsClear().
*/
/**
@page AAL5_Implementation_Details Version
@copydoc AAL5_Version
*/
/**
@page aal5_intro Introduction
The AAL5 implementation will support 16 channels for transmit and 16 channels for
receive. Each of the transmit channels may have up to two transmit queues
associated with it. If two queues are used, Queue 0 is the high priority queue,
and Queue 1 is the low priority queue.
*/
/**
@page aal5_params AAL5 Configuration Parameters
AAL5 requires two device entries to be available in the configuration repository, named
@p "aal5" and @p "sar". The @p aal5 device entry must contain @p base (base address)
and @p int_line (interrupt number). The @p sar device entry must have both @p base
(base address) and @p reset_bit (reset bit).
@par Device Level Configuration Parameters
The following parameters are device-level parameters, which apply across all
channels. The value for these parameters may be modified by changing the value in the
configuration repository.
- "UniNni":
AAL5 network setting. 0 = UNI (default), 1 = NNI.
@par Channel Configuration Parameters
All AAL5 channel parameters may also be configured through the @c ChannelSetup() interface.
Following is the list of @p CHANNEL_INFO members that may be modified by the driver when
calling @c ChannelSetup(). The driver may provide a value of 0xFFFFFFFF for any channel
parameter to select a default value for the parameter. The driver should at a minimum
configure @p Vci and @p Vpi. The usage of all parameters beginning with TxVc_,
TxVp_, RxVc_, RxVp_ is described in greater detail in the SAR Firmware Spec.
These parameters are mainly associated with QoS and OAM functionality.
- "RxNumBuffers":
The number of Rx buffer descriptors to allocate for Ch.
- "RxBufSize":
Size (in bytes) for each Rx buffer.
- "RxBufferOffset":
Number of bytes to offset rx data from start of buffer (must be less than buffer size).
- "RxServiceMax":
Maximum number of packets to service at one time.
- "TxNumBuffers":
The number of Tx buffer descriptors to allocate for Ch.
- "TxNumQueues":
Number of Tx queues for this channel (1-2). Choosing 2 enables a low priority SAR queue.
- "TxServiceMax":
Maximum number of packets to service at one time.
- "CpcsUU":
The 2-byte CPCS UU and CPI information.
- "Gfc":
Generic Flow Control. Used in ATM header of Tx packets.
- "Clp":
Cell Loss Priority. Used in ATM header of Tx packets.
- "Pti":
Payload Type Indication. Used in ATM header of Tx packets.
- "DaMask":
Specifies whether credit issuance is paused when Tx data not available. The default value is 1,
and this value should NOT be changed unless you have a complete understand of the outcome. When set to 0, CBR and VBR channels will not exhibit the desired functionality.
- "Priority":
Priority bin this channel will be scheduled within.
- "PktType":
0=AAL5,1=Null AAL,2=OAM,3=Transparent,4=AAL2.
- "Vci":
Virtual Channel Identifier.
- "Vpi":
Virtual Path Identifier.
- "TxVc_AtmHeader":
In firmware OAM mode, this
is the ATM header to be appended to front of firmware generated VC OAM cells for
this channel. Note: To generate host OAM cells, call @c Send() with
the appropriate mode.
- "TxVc_CellRate":
Tx rate, set as clock ticks between transmissions (SCR for VBR, CBR for CBR).
- "TxVc_QosType":
0=CBR,1=VBR,2=UBR,3=UBRmcr.
- "TxVc_Mbs":
Min Burst Size in cells.
- "TxVc_Pcr":
Peak Cell Rate for VBR in clock ticks between transmissions.
- "TxVc_OamTc":
TC Path to transmit OAM cells for TX connections (0,1).
- "TxVc_VpOffset":
Offset to the OAM VP state table for TX connections. Channels with the same
VPI must have the same VpOffset value. Channels with different VPIs
must have unique VpOffset values.
- "RxVc_OamCh":
Channel to which to terminate received OAM cells to be forwarded to the Host
for either Host OAM mode, or when RxVc_OamToHost is enabled during Firmware
OAM mode.
- "RxVc_OamToHost":
Indicates whether to pass received unmatched OAM loopback cells to the host;
0=do not pass, 1=pass.
- "RxVc_AtmHeader":
ATM Header placed on firmware gen'd OAM cells for this channel on a Rx
connection (must be big endian with 0 PTI).
- "RxVc_OamTc":
TC Path to transmit OAM cells for RX connections (0,1).
- "RxVc_VpOffset":
Offset to the OAM VP state table for RX connections. Channels with the same
VPI must have the same VpOffset value. Channels with different VPIs
must have unique VpOffset values.
- "TxVp_OamTc":
TC Path to transmit OAM cells for TX VP connections (0,1).
- "TxVp_AtmHeader":
ATM Header placed on firmware gen'd VP OAM cells for this channel on a Tx VP
connection (must be big endian with 0 VCI).
- "RxVp_OamCh":
Channel to which to terminate received OAM cells to be forwarded to the Host
for either Host OAM mode, or when RxVc_OamToHost is enabled during Firmware
OAM mode.
- "RxVp_OamToHost":
Indicates whether to pass received unmatched OAM loopback cells to the host;
0=do not pass, 1=pass.
- "RxVp_AtmHeader":
In firmware OAM mode, this
is the ATM header to be appended to front of firmware generated VP OAM cells for
this channel. Note: To generate host OAM cells, call @c Send() with
the appropriate mode.
- "RxVp_OamTc":
TC Path to transmit OAM cells for RX VP connections (0,1).
- "RxVp_OamVcList":
This 32-bit field is one-hot encoded to indicate all the VC channels that are
associated with this VP channel. A value of 21 will indicate that VC
channels 0, 2, and 4 are associated with this VP channel.
- "FwdUnkVc":
Indicates whether or not to forward unknown VCI/VPI cells to the host. This
parameter only takes effect if the channel's PktType is Transparent(3).
1=forwarding enabled, 0=forwarding disabled.
*/
/**
@page aal5_details API Implementation Details
ATTENTION: Documentation given here supplements the documentation given in the general
CPHAL API section. The following details are crucial to correct usage of the
AAL5 CPHAL.
@par Receive()
The least significant byte of @p Mode contains the channel number. Bit 31
indicates whether or not the ATM header is present in the first fragment of
the packet. If bit 31 is set, the 4 byte ATM header (minus HEC) will be provided
in the first fragment, with the payload beginning in the second fragment. Currently,
this is the default behavior for host OAM and transparent mode packets.
Bits 17-16 indicate the packet type that is being received.
Mode Parameter Breakdown: <BR>
- 31 ATM Header In First Fragment (1=true, 0=false) <BR>
- 30-18 Unused. <BR>
- 17-16 Pkt Type. <BR>
- 0=AAL5 <BR>
- 1=PTI Based Null AAL <BR>
- 2=OAM <BR>
- 3=Transparent <BR>
- 15-08 Unused. <BR>
- 07-00 Channel Number.
@par Send()
The most significant 16 bits of the first fragment 'len' is used as the Offset
to be added to the packet. @c Send() will reserve this many bytes at the
beginning of the transmit buffer prior to the first byte of valid data.
For the @p Mode parameter, Bit 31 must be set if the user has sent a packet with
the ATM Header (minus HEC) embedded in the first 4 bytes of the first fragment data buffer.
The OS has the option of using a 4 byte first fragment containing only ATM header,
or concatenating the ATM Header in front of the data payload.
If Bit 31 is set, the ATM Header in the buffer is preserved and sent with
each cell of the packet. Otherwise, Send() will build the ATM header based on the
values of the Pti, Gfc, Clp, Vpi, and Vci parameters for the given channel.
Bits 17-16 are defined as the packet type. Bits 15-08 may be used to specify the
transmit queue to send the packet on. Only values 0 (high priority) and 1 (low
priority) are accepted. Bits 07-00 should be used to indicate the channel number
for the @c Send() operation. Valid channel numbers are 0-15.
Mode Parameter Breakdown: <BR>
- 31 ATM Header In Packet (1=true, 0=false) <BR>
- 30-18 Unused. <BR>
- 17-16 Pkt Type. <BR>
- 0=AAL5 <BR>
- 1=PTI Based Null AAL <BR>
- 2=OAM <BR>
- 3=Transparent <BR>
- 15-08 Transmit Queue. <BR>
- 07-00 Channel Number.
@par ChannelSetup()
The AAL5 @c ChannelSetup() always configures both the Tx and Rx side of the channel
connection in the same call.
@par ChannelTeardown()
Regardless of the channel teardown direction selected, the AAL5 CPHAL will always
teardown both the Tx and Rx side of the channel connection.
@par TeardownComplete()
The value for the @p Direction parameter should be ignored for the AAL5 implementation,
since both directions (Tx and Rx) are always torndown in response to a @c ChannelTeardown()
command.
@par Control() (HAL version)
Defined keys and actions. Unless otherwise stated, the data type
for Value is pointer to unsigned integer. The list is broken into
three groups, one group which can be used anytime, one group that should
be used before halOpen(), and one group which can only be used after
halOpen() (but before halClose()). For channelized parameters, replace
'Ch' with the integer number of a channel (ex. "Gfc.4" can be used to set
Gfc for channel 4).
MAY USE ANYTIME AFTER INIT (after halInit() is called):
- "Gfc.Ch". The OS may "Set" this value. Changing this value causes
the Gfc in each Tx ATM header for this channel to take on the new Gfc value.
- "Clp.Ch". The OS may "Set" this value. Changing this value causes
the Clp in each Tx ATM header for this channel to take on the new Clp value.
- "Pti.Ch". The OS may "Set" this value. Changing this value causes
the Pti in each Tx ATM header for this channel to take on the new Pti value.
- "CpcsUU.Ch". The OS may "Set" this value. Changing this value causes
the CpcsUU in each Tx ATM header for this channel to take on the new CpcsUU value.
- "OamMode". Specifies if host or firmware is performing OAM functions; 0 = Host OAM,
1 = Firmware OAM. When set, all SAR channels will be configured for
the selection, including AAL2 channels.
- "OamLbTimeout". Specifies the firmware OAM loopback timeout, in milliseconds.
- "DeviceCPID". The OS may "Set" this value. This is the OAM connection
point identifier. The OS should provide a pointer to an array of 4 32-bit
integers. Each word must be configured in big endian format.
- "FwdUnkVc.Ch". Indicates whether or not to forward unknown VCI/VPI cells to the host.
This parameter only takes effect if the channel's PktType is Transparent(3).
1=forwarding enabled, 0=forwarding disabled.
MAY USE ONLY BEFORE HAL IS OPEN (before halOpen() call):
- "StrictPriority". The OS may "Set" this value. Setting to 1 causes
a different interrupt processing routine to be used, which gives strict
priority to channels with lower numbers (channel 0 has highest priority).
The default handler gives equal priority to all channels.
- "MaxFrags". The OS may "Set" or "Get" this value. This defines the maximum
number of fragments that can be received by the AAL5 Rx port. The default
value for AAL5 is 46. This provides enough space to receive a maximum
length AAL5 packet (65,568 bytes) with the default buffer size of 1518 bytes, and
any amount of RxBufferOffset. If the buffer size is configured to be smaller,
the OS *MUST* modify this parameter according to the following formula:
((System Max AAL5 packet length)/(RxBufSize)) + 2. (The extra two fragments in
the formula allow for RxBufferOffset and one fragment for the ATM Header, used
when receiving host OAM or transparent mode packets)
MAY USE ONLY AFTER HAL IS 'OPEN' (after halOpen() call):
- "Stats;Level;Ch;Queue". The OS may "Get" Stats groups with this key, where
'Level' is an integer from 0-4, Ch is an integer from 0-15, and Queue is
an integer from 0-1. Note that Ch is not required for Level 4 stats, and Queue
is not required for Level 0, 3, and 4. The statistics functionality and return
value is described in the appendix entitled "Configuration and Control".
- "TxVc_CellRate.Ch". The OS may "Set" this value. Can be used to modify
CellRate for a channel on the fly.
- "TxVc_Mbs.Ch". The OS may "Set" this value. Can be used to modify
Mbs for a channel on the fly.
- "TxVc_Pcr.Ch". The OS may "Set" this value. Can be used to modify
Pcr for a channel on the fly.
- "PdspEnable". The OS may "Set" this value. Value 0 disables the PDSP.
Value 1 enables to PDSP.
- "DeviceCPID". The OS may "Set" this value. The Value should be an array
of 4 32-bit integers that comprise the CPID.
- "RxVc_RDICount.Ch". The OS may "Get" or "Set" this value. Get returns
the current RDI count for the VC channel. Set clears the counter, and the Value
is ignored.
- "RxVp_RDICount.Ch". The OS may "Get" or "Set" this value. Get returns
the current RDI count for the VP channel. Set clears the counter, and the Value
is ignored.
- "RxVc_AISseg.Ch". The OS may "Get" this value. This is an indication of
AIS segment error for the VC channel.
- "RxVp_AISseg.Ch". The OS may "Get" this value. This is an indication of
AIS segment error for the VP channel.
- "RxVc_AISetoe.Ch". The OS may "Get" this value. This is an indication of
AIS end-to-end error for the VC channel.
- "RxVp_AISetoe.Ch". The OS may "Get" this value. This is an indication of
AIS end-to-end error for the VP channel.
- "RxVc_OamCh.Ch". The OS may "Set" this value. Channel to which to terminate
received OAM cells to be forwarded to the Host for either Host OAM mode, or when
RxVc_OamToHost is enabled during Firmware OAM mode.
- "RxVp_OamCh.Ch". The OS may "Set" this value. Channel to which to terminate
received OAM cells to be forwarded to the Host for either Host OAM mode, or when
RxVp_OamToHost is enabled during Firmware OAM mode.
- "F4_LB_Counter". The OS may "Get" this value. This is a count of the number
of near-end F4 loopbacks performed by the PDSP in firmware OAM mode.
- "F5_LB_Counter". The OS may "Get" this value. This is a count of the number
of near-end F5 loopbacks performed by the PDSP in firmware OAM mode.
- "TxVc_AtmHeader.Ch". The OS may "Set" this value. In firmware OAM mode, this
is the ATM header to be appended to front of firmware generated VC OAM cells for
this channel. In host OAM mode, this is used as the ATM header to be appended
to front of host generated VC OAM cells for this channel. It must be configured
as big endian with PTI=0. Note: To generate host OAM cells, call @c Send() with
the appropriate mode.
- "TxVp_AtmHeader.Ch". The OS may "Set" this value. In firmware OAM mode, this
is the ATM header to be appended to front of firmware generated VP OAM cells for
this channel. In host OAM mode, this is used as the ATM header to be appended
to front of host generated VP OAM cells for this channel. It must be configured
as big endian with VCI=0. Note: To generate host OAM cells, call @c Send() with
the appropriate mode.
- "PdspEnable". The OS may "Set" this value. Controls whether or not the PDSP is
allowed to fetch new instructions. The PDSP is enabled by the CPHAL during Open(),
and disabled during Close(). 0 = disabled, 1 = enabled.
- "TxFlush". The OS may "Set" this value. This may be used to flush all or part
of a given transmit queue on a given channel. The Value parameter is treated as
a pointer to an unsigned int. The unsigned int should be broken into fields as
follows: bits 31-16 = NumToKeep, bits 15-8 = Queue, bits 7-0 = Channel. "NumToKeep"
is the number of currently queued packets to allow, the rest will be flushed.
"Queue" selects the high or low priority queue for the channel, 0=high priority,
1=low priority. The number of packets flushed is returned through the Control()
call.
@par Control() (OS version)
Defined keys and actions:
- "Firmware". The CPHAL will perform a "Get" action for the key "Firmware". A pointer
to a pointer is passed in @p Value. The OS must modify the referenced pointer to point
to the firmware.
- "FirmwareSize". The CPHAL will perform a "Get" action for the key "FirmwareSize".
The OS must place the firmware size in the memory pointed at by @p Value.
- "OamLbResult". When a channel that is in firmware OAM mode is commanded to perform
a loopback function, the result of the loopback generates an interrupt that is handled
by the OS like any other interrupt. The CPHAL, upon servicing the interrupt, will call
osControl with this key, and an action of "Set". The @p Value parameter will be a
pointer to the integer result. 1 = pass, 0 = fail.
- "SarFreq". The CPHAL will perform a "Get" action for this key. The OS should place
the SAR frequency (in Hz) in the memory pointed at by @p Value.
*/
/**
@page aal5_stats AAL5 Specific Statistics
Statistics level '0' contains all AAL5 specific statistics. The following values will
be obtained when requesting stats level 0:
- "Crc Errors". Number of CRC errors reported by SAR hardware. Incremented for received
packets that contain CRC errors.
- "Len Errors". Number of length errors reported by SAR hardware. Incremented for received
packets that are in excess of 1366 cells.
- "Abort Errors". Number of abort errors reported by SAR hardware.
- "Starv Errors". Number of buffer starvation errors reported by SAR hardware. Incremented
when a part or all of a buffer cannot be received due to lack of RX buffer resources. The SAR
drops all cells associated with the packet for each buffer starvation error that occurs.
*/
/* register files */
#include "cp_sar_reg.h"
#define _CPHAL_AAL5
#define _CPHAL
#define _CPPI_TEST /** @todo remove for release */
#define __CPHAL_CPPI_OFFSET /* support use of offset */
/* OS Data Structure definitions */
typedef void OS_PRIVATE;
typedef void OS_DEVICE;
typedef void OS_SENDINFO;
typedef void OS_RECEIVEINFO;
typedef void OS_SETUP;
/* CPHAL Data Structure definitions */
typedef struct hal_device HAL_DEVICE;
typedef struct hal_private HAL_PRIVATE;
typedef struct hal_private HAL_RECEIVEINFO;
/* include CPHAL header files here */
#ifdef AR7_EFM
#include "tn7efm.h"
#endif
#include "cpcommon_cpaal5.h"
#include "cpswhal_cpaal5.h"
#include "aal5sar.h"
#include "cpcommon_cpaal5.c"
#define CR_SERVICE (170-1)
#define UTOPIA_PAUSE_REG (*(volatile bit32u *)0xa4000000)
/*
these masks are for the mode parameter used in halSend/OsReceive
(may move these elsewhere)
*/
#define CH_MASK 0xff
#define PRI_MASK 0x10000
/* Rcb/Tcb Constants */
#define CB_SOF_BIT (1<<31)
#define CB_EOF_BIT (1<<30)
#define CB_SOF_AND_EOF_BIT (CB_SOF_BIT|CB_EOF_BIT)
#define CB_OWNERSHIP_BIT (1<<29)
#define CB_EOQ_BIT (1<<28)
#define CB_SIZE_MASK 0x0000ffff
#define CB_OFFSET_MASK 0xffff0000
#define RCB_ERRORS_MASK 0x03fe0000
#define RX_ERROR_MASK 0x000f0000
#define CRC_ERROR_MASK 0x00010000
#define LENGTH_ERROR_MASK 0x00020000
#define ABORT_ERROR_MASK 0x00040000
#define STARV_ERROR_MASK 0x00080000
#define TEARDOWN_VAL 0xfffffffc
/* interrupt vector masks */
#define TXH_PEND 0x01000000
#define TXL_PEND 0x02000000
#define RX_PEND 0x04000000
#define STS_PEND 0x08000000
#define AAL2_PEND 0x10000000
#define INT_PENDING (TXH_PEND | TXL_PEND | RX_PEND | STS_PEND | AAL2_PEND)
#define STS_PEND_INVEC 0x0001F000
#define RX_PEND_INVEC 0x00000F00
#define TXL_PEND_INVEC 0x000000F0
#define TXH_PEND_INVEC 0x0000000F
#define AIS_SEG_MASK 0x1 /* +01.02.00 */
#define AIS_SEG_SHIFT 0 /* +01.02.00 */
#define AIS_ETOE_MASK 0x20000 /* +01.02.00 */
#define AIS_ETOE_SHIFT 17 /* +01.02.00 */
#define RDI_CNT_MASK 0xffff0000 /* +01.02.00 */
#define RDI_CNT_SHIFT 16 /* +01.02.00 */
#ifdef AR7_EFM
extern int g_efm_proc_ctl;
#endif
#ifdef EFM_DEBUG
//extern int sprintf ( char * buffer, const char * format, ...);
int disp_TCB_Queue_detail(char *buf, int count, int chan, HAL_DEVICE *pSarHalDev, int Queue)
{
int len = 0;
int limit = count - 80;
HAL_TCB *pTcbPool;
extern int disp_Hal_Device (char *buf, int count, CPSAR_DEVICE *pSarHalDev);
if (len <= limit)
len += sprintf (buf + len,"pTcbStart=%08x\n", (unsigned int) pSarHalDev->TcbStart[chan][Queue]);
if (len <= limit)
len += sprintf(buf + len,"TxActQueueCount=%d\n", pSarHalDev->TxActQueueCount[chan][Queue]);
pTcbPool = pSarHalDev->TcbPool[chan][Queue];
if (len <= limit)
len += sprintf(buf + len,"pTcbPool=%08x", (unsigned int) pTcbPool);
while (pTcbPool != NULL)
{
pTcbPool = pTcbPool->Next;
if (len <= limit)
len += sprintf(buf + len,"->%08x", (unsigned int) pTcbPool);
}
if (len <= limit)
len+= sprintf(buf + len,"\nTxActQueueHead=%08x\n", (unsigned int) pSarHalDev->TxActQueueHead[chan][Queue]);
if (len <= limit)
len+= sprintf(buf + len,"TxActQueueTail=%08x\n", (unsigned int) pSarHalDev->TxActQueueTail[chan][Queue]);
if (len <= limit)
len+= sprintf(buf + len,"TxActive=%d\n", pSarHalDev->TxActive[chan][Queue]);
if (len <= limit)
len += sprintf (buf + len,"SarFrequency=%d\n", pSarHalDev->SarFrequency);
if (len <= limit)
{
len += sprintf (buf + len, "SarDev=%08x\n", pSarHalDev->SarDev);
len += disp_Hal_Device( buf+len, count, pSarHalDev->SarDev);
}
return len;
}
int disp_TCB_Queue(char *buf, int count, int chan, HAL_DEVICE *pSarHalDev, int Queue)
{
int len = 0;
int limit = count - 80;
if (len <= limit)
len+= sprintf(buf + len, "%2d.%d %08x %08x %08x %08x %08x %08x\n", chan, Queue,
(unsigned int) pSarHalDev->TcbStart[chan][Queue],
pSarHalDev->TxActQueueCount[chan][Queue],
(unsigned int) pSarHalDev->TcbPool[chan][Queue],
(unsigned int) pSarHalDev->TxActQueueHead[chan][Queue],
(unsigned int) pSarHalDev->TxActQueueTail[chan][Queue],
(unsigned int) pSarHalDev->TxActive[chan][Queue]);
return len;
}
int disp_TCB_detail(char *buf, int count, void *Tcb_addr)
{
int len = 0;
int limit = count - 80;
HAL_TCB *pTcb= (HAL_TCB *) Tcb_addr;
if (len <= limit)
len+= sprintf(buf + len, "pTcb=%08x, sizeof(HAL_TCB)=%d (%02x)\n", (unsigned int) pTcb, sizeof(HAL_TCB), sizeof(HAL_TCB));
if (len <= limit)
len+= sprintf(buf + len, " HNext=%08x\n", pTcb->HNext);
if (len <= limit)
len+= sprintf(buf + len, " BufPtr=%08x\n", pTcb->BufPtr);
if (len <= limit)
len+= sprintf(buf + len, " Off_BLen=%08x\n", pTcb->Off_BLen);
if (len <= limit)
len+= sprintf(buf + len, " mode=%08x\n", pTcb->mode);
if (len <= limit)
len+= sprintf(buf + len, " AtmHeader=%08x\n", pTcb->AtmHeader);
if (len <= limit)
len+= sprintf(buf + len, " Word5=%08x\n", pTcb->Word5);
if (len <= limit)
len+= sprintf(buf + len, " Res6=%08x\n", pTcb->Res6);
if (len <= limit)
len+= sprintf(buf + len, " Res7=%08x\n", pTcb->Res7);
if (len <= limit)
len+= sprintf(buf + len, " Next=%08x\n", (unsigned int) pTcb->Next);
if (len <= limit)
len+= sprintf(buf + len, " OsInfo=%08x\n", (unsigned int) pTcb->OsInfo);
if (len <= limit)
len+= sprintf(buf + len, " Eop=%08x\n", (unsigned int) pTcb->Eop);
return len;
}
int disp_chan_detail(char *buf, int count, int chan, HAL_DEVICE *pSarHalDev)
{
int len = 0;
int limit = count - 80;
CHANNEL_INFO *pch;
pch = &pSarHalDev->ChData[chan];
if (len <= limit)
len+= sprintf (buf+len, "chan%d\n", chan);
if (len<= limit)
len+= sprintf (buf+len, "RxBufSize=%d, RxBufferOffset=%d, RxNumBuffers=%d, RxServiceMax=%d\n",
pch->RxBufSize, pch->RxBufferOffset, pch->RxNumBuffers, pch->RxServiceMax);
if (len<= limit)
len+= sprintf (buf+len, "TxNumBuffers=%d, TxNumQueues=%d, TxServiceMax=%d\n",
pch->TxNumBuffers, pch->TxNumQueues, pch->TxServiceMax);
return len;
}
int disp_RCB_Queue_detail(char *buf, int count, int chan, HAL_DEVICE *pSarHalDev)
{
int len = 0;
int limit = count - 80;
HAL_RCB *pRcbPool, *pRcbActQueue;
if (len<= limit)
len+= sprintf (buf + len, "pRcbStart=%08x\n", (unsigned int) pSarHalDev->RcbStart[chan]);
if (len<= limit)
len+= sprintf (buf + len, "RxActQueueCount=%d\n", pSarHalDev->RxActQueueCount[chan]);
pRcbPool = pSarHalDev->RcbPool[chan];
if (len<= limit)
len+= sprintf (buf + len, "pRcbPool=%08x", (unsigned int) pRcbPool);
while (pRcbPool != NULL)
{
pRcbPool = pRcbPool->Next;
len += sprintf (buf + len, "->%08x", (unsigned int) pRcbPool);
}
if (len<=limit)
len+= sprintf(buf+len, "\n");
if (len<=limit)
len+= sprintf(buf+len, "RxActQueueHead=%08x", (unsigned int) pSarHalDev->RxActQueueHead[chan]);
pRcbActQueue= pSarHalDev->RxActQueueHead[chan];
while (pRcbActQueue != NULL)
{
pRcbActQueue = pRcbActQueue->Next;
if (len<=limit)
len+= sprintf(buf+len, "->%08x", (unsigned int) pRcbActQueue);
}
if (len<= limit)
len+= sprintf(buf+len,"\n");
if (len<= limit)
len+= sprintf(buf+len, "RxActQueueTail=%08x\n", (unsigned int) pSarHalDev->RxActQueueTail[chan]);
if (len<= limit)
len+= sprintf(buf+len, "RxActive=%d\n", pSarHalDev->RxActive[chan]);
return len;
}
#endif
/*
* This function takes a vpi/vci pair and computes the 4 byte atm header
* (minus the HEC).
*
* @param vpi Virtual Path Identifier.
* @param vci Virtual Channel Identifier.
*
* @return A properly formatted ATM header, without the HEC.
*/
static int atmheader(int gfc, int vpi, int vci, int pti, int clp)
{
int itmp;
itmp=0;
/* UNI Mode uses the GFC field */
itmp |= ((gfc & 0xF) << 28);
itmp |= ((vpi & 0xFF) << 20);
/* if NNI Mode, no gfc and larger VPI */
/*itmp |= ((vpi & 0xFFF) << 20);*/
itmp|=((vci & 0xFFFF) << 4);
itmp|=((pti & 0x7) << 1);
itmp|=(clp & 0x1);
return(itmp);
}
#include "cppi_cpaal5.c"
/*
* Re-entrancy Issues
* In order to ensure successful re-entrancy certain sections of the
* CPHAL code will be bracketed as Critical.
* The OS will provide the function Os.CriticalSection(BOOL), which
* will be passed a TRUE to enter the Critical Section and FALSE to exit.
*/
/*
* @ingroup CPHAL_Functions
* Clears the statistics information.
*
* @param HalDev CPHAL module instance. (set by xxxInitModule())
*
* @return 0 OK, Non-zero not OK
*/
static int StatsClear(HAL_DEVICE *HalDev)
{
int i;
#ifdef AR7_EFM
int num_chan = (HalDev->EFM_mode ? NUM_EFM_CHAN : NUM_AAL5_CHAN);
#endif
#ifdef __CPHAL_DEBUG
if (DBG(0))
{
dbgPrintf("[aal5]StatsClear(HalDev:%08x)\n", (bit32u)HalDev);
osfuncSioFlush();
}
#endif
#ifdef AR7_EFM
for (i=0; i<num_chan; i++)
#else
/* clear stats */
for (i=0; i<NUM_AAL5_CHAN; i++)
#endif
{
HalDev->Stats.CrcErrors[i]=0;
HalDev->Stats.LenErrors[i]=0;
HalDev->Stats.DmaLenErrors[i]=0;
HalDev->Stats.AbortErrors[i]=0;
HalDev->Stats.StarvErrors[i]=0;
HalDev->Stats.TxMisQCnt[i][0]=0;
HalDev->Stats.TxMisQCnt[i][1]=0;
HalDev->Stats.RxMisQCnt[i]=0;
HalDev->Stats.RxEOQCnt[i]=0;
HalDev->Stats.TxEOQCnt[i][0]=0;
HalDev->Stats.TxEOQCnt[i][1]=0;
HalDev->Stats.RxPacketsServiced[i]=0;
HalDev->Stats.TxPacketsServiced[i][0]=0;
HalDev->Stats.TxPacketsServiced[i][1]=0;
HalDev->Stats.TxMaxServiced[i][0]=0;
HalDev->Stats.TxMaxServiced[i][1]=0;
}
HalDev->Stats.RxTotal=0;
HalDev->Stats.TxTotal=0;
HalDev->Stats.RxMaxServiced=0;
return (EC_NO_ERRORS);
}
/*
* Returns statistics information.
*
* @param HalDev CPHAL module instance. (set by xxxInitModule())
*
* @return 0
*/
/*
static STAT_INFO* StatsGet(HAL_DEVICE *HalDev)
{
STAT_INFO* MyStats = &HalDev->Stats;
#ifdef __CPHAL_DEBUG
if (DBG(0))
{
dbgPrintf("[aal5]StatsGet(HalDev:%08x)\n", (bit32u)HalDev);
osfuncSioFlush();
}
#endif
dbgPrintf("HAL Stats:\n");
DispStat(HalDev, "Rx Total",MyStats->RxTotal);
DispStat(HalDev, "Tx Total",MyStats->TxTotal);
DispStat(HalDev, "Rx Peak",MyStats->RxMaxServiced);
DispStat(HalDev, "TxH Peak",MyStats->TxMaxServiced[0][0]);
DispStat(HalDev, "TxL Peak",MyStats->TxMaxServiced[0][1]);
DispChStat(HalDev, "CrcErr",&MyStats->CrcErrors[0],1);
DispChStat(HalDev, "LenErr",&MyStats->LenErrors[0],1);
DispChStat(HalDev, "DmaLenErr",&MyStats->DmaLenErrors[0],1);
DispChStat(HalDev, "AbortErr",&MyStats->AbortErrors[0],1);
DispChStat(HalDev, "StarvErr",&MyStats->StarvErrors[0],1);
DispChStat(HalDev, "TxH MisQ Cnt",&MyStats->TxMisQCnt[0][0],2);
DispChStat(HalDev, "TxL MisQ Cnt",&MyStats->TxMisQCnt[0][1],2);
DispChStat(HalDev, "Rx MisQ Cnt",&MyStats->RxMisQCnt[0],1);
DispChStat(HalDev, "Rx EOQ Cnt",&MyStats->RxEOQCnt[0],1);
DispChStat(HalDev, "TxH EOQ Cnt",&MyStats->TxEOQCnt[0][0],2);
DispChStat(HalDev, "TxL EOQ Cnt",&MyStats->TxEOQCnt[0][1],2);
DispChStat(HalDev, "Rx Pkts",&MyStats->RxPacketsServiced[0],1);
DispChStat(HalDev, "TxH Pkts",&MyStats->TxPacketsServiced[0][0],2);
DispChStat(HalDev, "TxL Pkts",&MyStats->TxPacketsServiced[0][1],2);
return (&HalDev->Stats);
}
*/
#ifdef __CPHAL_DEBUG
void dbgChannelConfigDump(HAL_DEVICE *HalDev, int Ch)
{
CHANNEL_INFO *HalCh = &HalDev->ChData[Ch];
dbgPrintf(" [aal5 Inst %d, Ch %d] Config Dump:\n", HalDev->Inst, Ch);
dbgPrintf(" TxNumBuffers :%08d, TxNumQueues :%08d\n",
HalCh->TxNumBuffers, HalCh->TxNumQueues);
dbgPrintf(" RxNumBuffers :%08d, RxBufSize :%08d\n",
HalCh->RxNumBuffers, HalCh->RxBufSize);
dbgPrintf(" TxServiceMax :%08d, RxServiceMax:%08d\n",
HalCh->TxServiceMax, HalCh->RxServiceMax);
dbgPrintf(" RxBufferOffset:%08d, DaMask :%08d\n",
HalCh->RxBufferOffset, HalCh->DaMask);
dbgPrintf(" CpcsUU :%08d, Gfc :%08d\n",
HalCh->CpcsUU, HalCh->Gfc);
dbgPrintf(" Clp :%08d, Pti :%08d\n",
HalCh->Clp, HalCh->Pti);
dbgPrintf(" Priority :%08d, PktType :%08d\n",
HalCh->Priority, HalCh->PktType);
dbgPrintf(" Vci :%08d, Vpi :%08d\n",
HalCh->Vci, HalCh->Vpi);
dbgPrintf(" TxVc_CellRate :%08d, TxVc_QosType:%08d\n",
HalCh->TxVc_CellRate, HalCh->TxVc_QosType);
dbgPrintf(" TxVc_Mbs :%08d, TxVc_Pcr :%08d\n",
HalCh->TxVc_Mbs, HalCh->TxVc_Pcr);
dbgPrintf(" TxVc_AtmHeader:%08d\n",
HalCh->TxVc_AtmHeader);
osfuncSioFlush();
}
#endif
/*
* Retrieves channel parameters from configuration file. Any parameters
* which are not found are ignored, and the HAL default value will apply,
* unless a new value is given through the channel structure in the call
* to ChannelSetup.
*/
static int ChannelConfigGet(HAL_DEVICE *HalDev, CHANNEL_INFO *HalChn)
{
unsigned int Ret, Value, Ch = HalChn->Channel;
OS_FUNCTIONS *OsFunc = HalDev->OsFunc;
void *ChInfo;
#ifdef __CPHAL_DEBUG
if (DBG(0))
{
dbgPrintf("[aal5]ChannelConfigGet(HalDev:%08x, HalChn:%08x)\n", (bit32u)HalDev,
(bit32u)HalChn);
osfuncSioFlush();
}
#endif
#ifdef AR7_EFM
if (HalDev->EFM_mode)
{
HalDev->ChData[Ch].TxNumBuffers = 32;
HalDev->ChData[Ch].TxNumQueues = 2;
HalDev->ChData[Ch].TxServiceMax = 32;
HalDev->ChData[Ch].RxNumBuffers = 16;
HalDev->ChData[Ch].RxBufferOffset = 0;
HalDev->ChData[Ch].RxBufSize = 1582;
HalDev->ChData[Ch].RxServiceMax = 16;
return EC_NO_ERRORS;
}
#endif
Ret=OsFunc->DeviceFindParmValue(HalDev->DeviceInfo, channel_names[Ch], &ChInfo);
if (Ret) return (EC_AAL5|EC_FUNC_CHSETUP|EC_VAL_CH_INFO_NOT_FOUND);
/* i don't care if a value is not found because they are optional */
Ret=OsFunc->DeviceFindParmUint(ChInfo, "TxNumBuffers", &Value);
if (!Ret) HalDev->ChData[Ch].TxNumBuffers = Value;
Ret=OsFunc->DeviceFindParmUint(ChInfo, "TxNumQueues", &Value);
if (!Ret) HalDev->ChData[Ch].TxNumQueues = Value;
Ret=OsFunc->DeviceFindParmUint(ChInfo, "TxServiceMax", &Value);
if (!Ret) HalDev->ChData[Ch].TxServiceMax = Value;
Ret=OsFunc->DeviceFindParmUint(ChInfo, "RxNumBuffers", &Value);
if (!Ret) HalDev->ChData[Ch].RxNumBuffers = Value;
Ret=OsFunc->DeviceFindParmUint(ChInfo, "RxBufferOffset", &Value);
if (!Ret) HalDev->ChData[Ch].RxBufferOffset = Value;
Ret=OsFunc->DeviceFindParmUint(ChInfo, "RxBufSize", &Value);
if (!Ret) HalDev->ChData[Ch].RxBufSize = Value;
Ret=OsFunc->DeviceFindParmUint(ChInfo, "RxServiceMax", &Value);
if (!Ret) HalDev->ChData[Ch].RxServiceMax = Value;
Ret=OsFunc->DeviceFindParmUint(ChInfo, "CpcsUU", &Value);
if (!Ret) HalDev->ChData[Ch].CpcsUU = Value;
Ret=OsFunc->DeviceFindParmUint(ChInfo, "Gfc", &Value);