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dsl_hal_api.c
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dsl_hal_api.c
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/*******************************************************************************
* FILE PURPOSE: DSL Driver API functions for Sangam
*
********************************************************************************
* FILE NAME: dsl_hal_api.c
*
* DESCRIPTION:
* Contains basic DSL HAL APIs for Sangam
*
*
* (C) Copyright 2001-02, Texas Instruments, Inc.
* History
* Date Version Notes
* 06Feb03 0.00.00 RamP Original Version Created
* 10Mar03 0.00.01 RamP Initial Revision for Modular Code Branch
* 19Mar03 0.00.02 RamP Fixed DSL and DSP Version API Structures
* 20Mar03 0.00.03 RamP Changed byteswap function names
* 21Mar03 0.00.03 RamP/ZT Malloc for DSP f/w done in dslStartup
* 25Mar03 0.00.04 RamP Removed statistics used only by SWTC
* Created Checkpoint 3
* 26Mar03 0.00.05 RamP Added Memory allocation for fwimage in
* dslStartup function.
* 07Apr03 0.00.06 RamP Implemented new error reporting scheme
* Changed Commenting to C style only
* 09Apr03 0.00.07 RamP Reorganized code to delete POST_SILICON
* 10Apr03 0.00.08 RamP Removed ptidsl from loadFWImage function
* moved size and fwimage initialization to
* dslStartup function
* 14Apr03 0.00.09 RamP Moved modemStateBitField processing to a
* support function; deleted stateHistory
* renamed the REG32 macro
* 15Apr03 0.00.10 RamP Changed firmware allocate to shim_
* osAllocateVMemory function
* 15Apr03 0.00.11 RamP Changed host version number to 07.00.00.01
* 16Apr03 0.00.12 RamP Modified return condition on dslShutdown
* 16Apr03 0.00.13 RamP Changed host version number to 07.00.00.02
* 21Apr03 0.01.00 RamP Cleaned up dslShutdown function
* Added new function calls to allocate
* (Alpha) /free overlay pages for different OS
* Fixed typecasting for allocate/free fxns
* Added Interrupt Acknowledge logic
* 22Apr03 0.01.01 RamP Moved acknowledgeInterrupt into api
* Added static global for intr source
* 24Apr03 0.01.02 RamP Added processing for OVERLAY_END in
* DSP message handlers, verified crc32
* recovery for overlays
* 28Apr03 0.01.03 RamP Removed global variable intrSource
* Added parameter to handleInterrupt fxn
* (Alpha Plus) to indicate interrupt source
* Changed version number to 01.00.01.00
* Fixed setTrainingMode function problem
* 07May03 0.01.04 RamP Removed delineation state check in
* message handling functions, added more
* safety for setting lConnected in TC_SYNC
* Changed version number to 01.00.01.01
* 14May03 0.01.05 RamP Added 3 Switchable Hybrid APIs
* Added additional statistics us/ds TxPower,
* us margin,attenuation, us/ds bitallocation
* moved versioning to dsl_hal_version.h
* 14May03 0.01.06 RamP Fixed problem with CMsgs2 parsing
* 20May03 0.01.07 RamP Added Inner/Outer pair API support. Added
* dying gasp message.
* 29May03 0.01.08 ZT/RamP Added memory optimizations for overlay pages
* and coProfiles; added functions to free,
* reload overlays and profiles
* 04Jun03 0.01.09 RamP Added tick counters, fail states reporting
* Made statistics fixes for higher data rates
* Added Margin per tone to statistics
* Added configuration checks for trellis/FEC
* 06Jun03 0.01.10 RamP Added LED, STM Bert, dGasp LPR Config APIs
* Modified interrupt acknowledge logic
* Added current hybrid flag as statistic
* 09Jun03 0.01.11 RamP Added function to send dying Gasp to Modem
* fixed problem with reading OamNegoPara var
* (Beta) fixed problem with reading current config
* Added function to configure ATM Bert
* fixed memory leak due to coProfiles
* Added us/ds R/S FEC statistics
* Added additional config capability for LED
* fixed problem in free memory for CO profiles
* 18Jul03 0.01.12 RamP Fixed problem with reading modemEnv structure
* affects LED, DGaspLpr APIs
* Sending Dying Gasp from shutdown function
* 01Aug03 0.01.13 RamP Added preferred training mode to statistics
* 13Aug03 0.01.14 MCB Set rev id for D3/R1.1 (ADSL2).
* 21Aug03 0.01.15 RamP Added g.hs and aoc bitswap message gathering
* Added new references to bits n gains table
* Decoupled modem idle/retrain from pair select
* Added line length and gross gain to statistics
* 29Sep03 0.01.16 RamP Replaced advcfg function calls with support
* module function switches
* 01Oct03 0.01.17 RamP Added enum translation to set training mode
* & to read statistics
* 08Oct03 0.01.18 RamP Fixed problems with usTxPower statistic in
* Annex B target, fixed problem with Trellis
* 12Oct03 0.01.19 RamP Added API calls to gather ADSL2 Messages
* 29Oct03 0.01.20 RamP Restored TC_SYNC detect logic
* 30Oct03 0.01.21 RamP Removed Scaling factor for adsl2DSConRate
* Setting Showtime state upon DSP_ACTIVE
* 14Nov03 0.01.22 RamP Fixed scaling for usTxPower & dsTxPower
* 14Nov03 0.01.23 RamP Added logic to gather CRates1/RRates1
* by parsing DSP_CRATES1
* 20Nov03 0.01.24 RamP Added generic & interface Read
* and Write functions to read from
* DSP - Host Interface
* 24Nov03 0.01.25 RamP Modified interface Read/Write functions
* to seperate element offsets from pointers
* 19Dec03 0.01.26 RamP Modified pointer accessing problems with
* block read functions
* 26Dec03 0.01.27 RamP Made ghsIndex a local variable & added
* check to avoid buffer overflow
* 30Dec03 0.01.28 RamP Added generic mailbox command function
* 26Feb04 0.01.29 RamP Added code to get error statistics
* 02Mar04 0.01.30 RamP Changed overlay page number constant to
* refer to the host interface constant
* 05Mar04 0.01.31 RamP Scaled dsNoise factors to get dB output
* 01Apr04 0.01.32 RamP Overflow Check for Training Fails added
* 20Apr04 0.01.33 RamP decoupled overlay page check from host
* interface, added scratch memory support
* 27Apr04 0.01.34 RamP Fixed double-swap problem with Tx Power
* 29Apr04 0.01.35 RamP Overflow check for Training Fails added
* Scaled all statistics arrays for ADSL2+
* added detection for ADSL2+ in gather
* statistics API
* 04May04 0.01.36 RamP Reset bState based on DSP_IDLE added
* 04May04 0.01.37 RamP Removed Scaling factor for adsl2USConRate
* 14May04 0.01.38 RamP Split statistics function to avoid stack
* overflow problem due to local variables
* Modified type & equation for power cutback
* Updated statistics for ADSL2+
* 17May04 0.01.39 RamP Must #IFDEF out dslhal_api_getAdvancedStats()
* function call body, instead of function call.
* Must #IFDEF out dslhal_staticapi_getHlog().
* 02Aug04 0.01.40 RamP Fixed problem with DSL Activitiy LED config.
* Fixed initialization issue for currAddr in
* dsp interface read/write APIs.
* 26Aug04 0.01.41 Brian Made changes to support switching DSP
* frequency to 250Mhz
* 22Sep04 0.01.42 RamP Corrected fast/intlv determination
* for ADSL2/2+ training modes
* 06Oct04 0.01.43 RamP Added API functions to configure DSL PHY
* features and to set DSP/MIPS as controller
* for these features
* 29Dec04 0.01.44 DW CQ 9356: Added some compiler tokens for commonly
* used numbers. Modified the feature-related APIs
* to use these. Added a parameter validity check
* in these APIs.
* 27Jan05 0.01.44 CPH Added Ohio250 support.
* 02Feb05 0.01.45 CPH Pull dev_host_interface.h out from dsl_hal_register.h
* 15Jan05 0.01.45 T.Leyrer Added support for maxBits configuration in
* each direction
* 29Mar05 0.01.46 CPH Restore dslhal_api_setMaxBitsPerCarrier as function
*
* 10May05 Arvind CQ 9605:Added a new API
* dslhal_api_setTrainingMode_BitField()
* for allowing the user to select from
* the dsl modes using bitfields.
* 14Jun05 CPH Added AnnexB & M support.
* - Extend dslhal_api_setTrainingMode_BitField()
* - Add dslhal_support_getTrainedModeEx()
* 29Jun05 CPH Optimization: consolidate dslhal_api_gatherStatistics() and
* dslhal_api_initStatistics()
* 7July05 CPH Optimization: consolidate dslhal_api_pollTrainingStatus() and
* dslhal_api_handleTrainingInterrupt()
*
* 10May05 Arvind CQ 9605: Added a new field in the
* tagTIOIDINFO structure, for allowing the user to
* select from the dsl modes using bitfields.
* 2June05 0.01.47 CPH CQ 9690:Preserve Preserve exisiting PRCR reset status
* for other pheripherals in dslhal_api_boostDspFrequency().
* 29Jun05 0.01.48 AV Fixed training mode statistics bug.
* 20Jul05 0.01.49 AV CQ 9802: Moved the order when the OHIO_250_MODE
* is selected relative to when the System PLL is
* initialized. Also, added the power down of the
* SAR, DSP and ADSLSS when the frequency is being
* boosted to 250MHz.
* 10Aug05 0.01.50 CPH Clean Up, fixed dsGains[] negative index problem.
* 5Sept05 0.01.60 CPH CQ9776: Added dslhal_api_getHLOGpsds(), dslhal_api_getQLNpsds(),
* and dslhal_api_getSNRpsds().
* 29Sept05 0.01.70 CPH Fixed ATM driver hang before showtime problem.
* 04Oct05 0.01.71 CPH Added 7100A1/A2 support.
* 7 Oct05 0.01.80 AV/CPH Changed dprintf to dgprintf for code size reduction.
* 03Nov05 0.01.80 Manjula CQ10037: Modified dslhal_api_setEocRevisionNumber to support
* Inventory command to set version number.
* 04Nov05 0.11.00 CPH Fixed T1413 mode got Zero DS/US rate when DSL_BIT_TMODE is set.
*
* 23Nov05 0.12.00 CPH Added set LPR when get DSP_GASP.
* 30Nov05 0.12.01 KM/JZ CQ10226: Added processing Loss of Framing (LOF) in
* dslhal_api_processMailBox(), and setting errored seconds in
* dslhal_api_gatherStatistics().
* 01Dec05 0.12.00 AV Fixed an issue with dslhal_api_boostDspFrequency(), where it
* sometimes would not boost the DSP frequency for Ohio chips.
* 08Aug06 0.13.00 GPet/CPH CQ 10242: Added CLI2Host support. (token:CLI2HOST_SUPPORT)*
* UR8_MERGE_START Report_SES Manjula K
* 14Mar06 0.14.00 MK CQ10369: Added code to report severly errored seconds in
* dslhal_api_gatherStatistics(
* UR8_MERGE_END Report_SES
* UR8_MERGE_START CQ10386 PeterHou
* 15Mar06 0.15.00 CPH CQ10386: Add SNR format comment to dslhal_api_getSNRGpsds().
* UR8_MERGE_END CQ10386
* UR8_MERGE_START GERALD_CQ_REDIRECT_BUGFIX2_20060328 Gerald
* 28Mar06 0.16.00 GPet CQ10411: Fixed CLIredirect reboot crash
* UR8_MERGE_END GERALD_CQ_REDIRECT_BUGFIX2_20060328
* UR8_MERGE_START CQ10481 Jack Zhang
* 21Apr06 0.16.00 Jack Zhang CQ10481: Selected Mode" in /proc/avalanche/avsar_modem_stats
* not displaying correct value
* UR8_MERGE_END CQ10481
* UR8_MERGE_START CQ10499 Jack Zhang
* 05May06 CQ10499: ATM Driver Cleanup/Improvement Umbrella
* UR8_MERGE_END CQ10499
* UR8_MERGE_START CQ10442 Manjula K
* 31May06 0.17.00 MK CQ10442: Added code to handle mailbox message for SRA in
* dslhal_api_processMailBox()
* UR8_MERGE_END CQ10442
* UR8_MERGE_START CQ10905 Jeremy L
* 05Sept06 CQ10905: Modified HAL to display TrainedPath
* UR8_MERGE_END CQ10905 correctly for ADSL2/2+
*
* UR8_MERGE_START CQ10880 Jack Zhang
* 8/30/06 JZ CQ10880: Add DSL HAL API for sending mailbox message for L3
* UR8_MERGE_END CQ10880*
// UR8_MERGE_START CQ11007 KCCHEN
// 09/26/06 KCCHEN CQ11007 : US SNR margin update
// UR8_MERGE_END CQ11007 KCCHEN
* UR8_MERGE_START CQ10978 Jack Zhang
* 10/4/06 JZ CQ10978: Request for the DSL Power Management Status Report
* UR8_MERGE_END CQ10978*
* UR8_MERGE_START CQ10979 Jack Zhang
* 10/4/06 JZ CQ10979: Request for TR-069 Support for RP7.1
* UR8_MERGE_END CQ10979*
// UR8_MERGE_START CQ11057 KCCHEN
// 10/12/06 Kuan-Chen Chen CQ11057: Request US PMD test parameters from CO side
// UR8_MERGE_END CQ11057 KCCHEN
* UR8_MERGE_START CQ11228 HZ
* 12/08/06 Hao Zhou CQ11228: Modify the DS Margin report to 0.1dB precision, also take care of
* possible negative values.
* UR8_MERGE_END CQ11228 HZ
* UR8_MERGE_START CQ11054 Jack Zhang
* 10/11/06 JZ CQ11054: Data Precision and Range Changes for TR-069 Conformance
* UR8_MERGE_END CQ11054*
* UR8_MERGE_START_END CQ11247_TR69_DS_LATN_SATN YW
* 12/18/06 Yan Wang CQ11247: TR069 range and precision changes for LATNds, SATNds
* UR8_MERGE_START CQ11227 KCCHEN
* 01/02/07 KuanChen Chen CQ11227: ADSL1 upstream max rate report. Customer wants to access the
* upstream max rate through the CoPMDTestParams_t struct.
* UR8_MERGE_END CQ11227 KCCHEN
* UR8_MERGE_START_END CQ11446 Nima :Added handling of BROWNOUT message for dying gasp
* UR8_MERGE_START_END CQ11341 Ram
* 03/05/07 Ram CQ11341: Changed the offset of the function dslhal_api_setPhyFeatureController
* to be the same as dslhal_api_enableDisablePhyFeatures. Although these
* two functions are now exactly identical, it has been maintained for
* consistency to legacy Customer API calls.
* Also updated dslhal_api_readPhyFeatureSettings to equate the content
* of phyEnableDisableWord & phyControlWord to avoid changing API struct
* which may cause change required to application data structure.
* UR8_MERGE_START_END CQ11579 Tim
* 03/29/07 Tim CQ11579: Allow SNR reads in ADSL1 and fixed the ADSL1 PCB calculation
* UR8_MERGE_START CQ11579 Jeremy : Corrected handling of usPowerCutback for ADSL1
* 04/02/07 included T1413 for if statement comparison
* UR8_MERGE_END CQ11579
* UR8_MERGE_START CQ11544 Tim
* 04/16/07 Tim CQ11544: Add support for uncancelled echo metric
* UR8_MERGE_START_END CQ11709 Tim
* 05/01/07 Tim CQ11709: Added support for AT&T priority 1 statistics
* UR8_MERGE_START_END CQ11803 KCCHEN/Ram
* 06/12/07 Ram CQ11803: Added new API to compute Delta US Attainable NDR
* UR8_MERGE_START CQ11813 Hao-Ting
* 06/08/07 Hao-Ting CQ11813:CLI redirect support in linux
* Mark unused function in linux use LINUX_CLI_SUPPORT flag
* UR8_MERGE_END CQ11813 Hao-Ting
* 09/12/07 EYin CQ11929: Added NFEC/INP/Lp/Rp reporting for both US and DS in
* dslhal_api_gatherStatistics()
* 09/15/07 CPH CQ11466 Added EFM support
* 09/27/07 EYin CQ11929: Added NFEC/INP/Lp/Rp reporting for only ADSL2/2+ mode.
******************************************************************************/
#include <dev_host_interface.h>
#include <dsl_hal_register.h>
#include <dsl_hal_support.h>
#ifndef NO_ADV_STATS
#include <dsl_hal_logtable.h>
#endif
#include <dsl_hal_version.h>
// UR8_MERGE_START CQ11054 Jack Zhang
static unsigned int highprecision_selected = 0; //By default we use low precision for backward compt.
// UR8_MERGE_END CQ11054*
static unsigned int hybrid_selected;
static unsigned int showtimeFlag = FALSE;
static unsigned char triggerDsp250MHZ;
static int dslhal_api_processMailBox(tidsl_t *ptidsl,
DEV_HOST_dspOamSharedInterface_t *p_dspOamSharedInterface, int intFlag);
/* CQ 9802: Number of power down retries. */
#ifndef PWR_DN_RETRYS
#define PWR_DN_RETRYS 3
#endif
#ifndef NO_ADV_STATS
static short dslhal_staticapi_getHlog(tidsl_t *ptidsl,unsigned int index);
#endif
// DW 12/29/04 CQ 9356 Common declarations
#define NUM_BYTES_PER_INT 4 // 32 bits to an integer
#define NUM_BYTES_PER_ADDRESS 4 // 32-bit addresses
#define NUM_PHY_FEATURE_LEVELS 3 // Pointer to a pointer to a structure format
// is used for Phy features
#define MAX_PHY_FEATURE_PARAMID 3 // Currently 4 parameter IDs exist:
// 0-1 for Phy features and 2-3 for Interop
// features.
#define DDI_RX_MSG_DELAY_OFFSET 1040
#define DDI_RX_MSG_LP_OFFSET 1116
#define DDI_TX_MSG_DELAY_OFFSET 268
#define DDI_TX_MSG_LP_OFFSET 292
#ifdef PRE_SILICON
/*********************************************/
/* Base Addresses */
/*********************************************/
#define DEV_MDMA_BASE 0x02000500
/*********************************************/
/* MC DMA Control Registers in DSL */
/*********************************************/
#define DEV_MDMA0_SRC_ADDR (DEV_MDMA_BASE + 0x00000000)
#define DEV_MDMA0_DST_ADDR (DEV_MDMA_BASE + 0x00000004)
#define DEV_MDMA0_CTL_ADDR (DEV_MDMA_BASE + 0x00000008)
#define DEV_MDMA1_SRC_ADDR (DEV_MDMA_BASE + 0x00000040)
#define DEV_MDMA1_DST_ADDR (DEV_MDMA_BASE + 0x00000044)
#define DEV_MDMA1_CTL_ADDR (DEV_MDMA_BASE + 0x00000048)
#define DEV_MDMA2_SRC_ADDR (DEV_MDMA_BASE + 0x00000080)
#define DEV_MDMA2_DST_ADDR (DEV_MDMA_BASE + 0x00000084)
#define DEV_MDMA2_CTL_ADDR (DEV_MDMA_BASE + 0x00000088)
#define DEV_MDMA3_SRC_ADDR (DEV_MDMA_BASE + 0x000000C0)
#define DEV_MDMA3_DST_ADDR (DEV_MDMA_BASE + 0x000000C4)
#define DEV_MDMA3_CTL_ADDR (DEV_MDMA_BASE + 0x000000C8)
#define DEV_MDMA0_SRC (*((volatile UINT32 *) DEV_MDMA0_SRC_ADDR))
#define DEV_MDMA0_DST (*((volatile UINT32 *) DEV_MDMA0_DST_ADDR))
#define DEV_MDMA0_CTL (*((volatile UINT32 *) DEV_MDMA0_CTL_ADDR))
#define DEV_MDMA1_SRC (*((volatile UINT32 *) DEV_MDMA1_SRC_ADDR))
#define DEV_MDMA1_DST (*((volatile UINT32 *) DEV_MDMA1_DST_ADDR))
#define DEV_MDMA1_CTL (*((volatile UINT32 *) DEV_MDMA1_CTL_ADDR))
#define DEV_MDMA2_SRC (*((volatile UINT32 *) DEV_MDMA2_SRC_ADDR))
#define DEV_MDMA2_DST (*((volatile UINT32 *) DEV_MDMA2_DST_ADDR))
#define DEV_MDMA2_CTL (*((volatile UINT32 *) DEV_MDMA2_CTL_ADDR))
#define DEV_MDMA3_SRC (*((volatile UINT32 *) DEV_MDMA3_SRC_ADDR))
#define DEV_MDMA3_DST (*((volatile UINT32 *) DEV_MDMA3_DST_ADDR))
#define DEV_MDMA3_CTL (*((volatile UINT32 *) DEV_MDMA3_CTL_ADDR))
/* MDMA control bits */
#define DEV_MDMA_START 0x80000000
#define DEV_MDMA_STOP 0x00000000
#define DEV_MDMA_STATUS 0x40000000
#define DEV_MDMA_DST_INC 0x00000000
#define DEV_MDMA_DST_FIX 0x02000000
#define DEV_MDMA_SRC_INC 0x00000000
#define DEV_MDMA_SRC_FIX 0x00800000
#define DEV_MDMA_BURST1 0x00000000
#define DEV_MDMA_BURST2 0x00100000
#define DEV_MDMA_BURST4 0x00200000
#define DEV_MDMA_LEN_SHF 2
#define DEV_MDMA_LEN_MASK 0x0000FFFF
#define DMA0 0
#define DMA1 1
#define DMA2 2
#define DMA3 3
#endif
#ifdef DMA
SINT32 getDmaStatus(UINT32 mask)
{
if(!(IFR & mask))
{
return DSLHAL_ERROR_NO_ERRORS;
}
else
{
ICR = mask ;
return 1 ;
}
}
void programMdma(UINT32 dma, UINT32 source, UINT32 destination, UINT32 length, UINT32 wait)
{
volatile UINT32 statusMask ;
switch(dma)
{
case DMA0:
{
DEV_MDMA0_SRC = source ;
DEV_MDMA0_DST = destination ;
DEV_MDMA0_CTL = (DEV_MDMA_START | DEV_MDMA_DST_INC | DEV_MDMA_SRC_INC |
DEV_MDMA_BURST1 | (length << DEV_MDMA_LEN_SHF)) ;
statusMask = 0x00000010 ;
}
break ;
case DMA1:
{
DEV_MDMA1_SRC = source ;
DEV_MDMA1_DST = destination ;
DEV_MDMA1_CTL = (DEV_MDMA_START | DEV_MDMA_DST_INC | DEV_MDMA_SRC_INC |
DEV_MDMA_BURST1 | (length << DEV_MDMA_LEN_SHF)) ;
statusMask = 0x00000020 ;
}
break ;
case DMA2:
{
DEV_MDMA2_SRC = source ;
DEV_MDMA2_DST = destination ;
DEV_MDMA2_CTL = (DEV_MDMA_START | DEV_MDMA_DST_INC | DEV_MDMA_SRC_INC |
DEV_MDMA_BURST1 | (length << DEV_MDMA_LEN_SHF)) ;
statusMask = 0x00000040 ;
}
break ;
case DMA3:
{
DEV_MDMA3_SRC = source ;
DEV_MDMA3_DST = destination ;
DEV_MDMA3_CTL = (DEV_MDMA_START | DEV_MDMA_DST_INC | DEV_MDMA_SRC_INC |
DEV_MDMA_BURST1 | (length << DEV_MDMA_LEN_SHF)) ;
statusMask = 0x00000080 ;
}
break ;
}
if(wait)
{
while(!(getDmaStatus(statusMask))) ;
}
}
#endif
// UR8_MERGE_START CQ11054 Jack Zhang
unsigned int dslhal_api_getHighPrecision()
{
return highprecision_selected;
}
void dslhal_api_setHighPrecision()
{
highprecision_selected = 1;
}
// UR8_MERGE_END CQ11054*
/******************************************************************************************
* FUNCTION NAME: dslhal_api_dslStartup
*
*******************************************************************************************
* DESCRIPTION: Entry point to initialize and load ax5 daughter board
*
* INPUT: PITIDSLHW_T *ppIHw
*
* RETURN: 0 --succeeded
* 1 --Failed
*
*****************************************************************************************/
int dslhal_api_dslStartup(PITIDSLHW_T *ppIHw)
{
ITIDSLHW_T *ptidsl;
int i;
int rc;
dgprintf(4,"dslhal_api_dslStartup() NEW 1\n");
ptidsl=(ITIDSLHW_T *)shim_osAllocateMemory(sizeof(ITIDSLHW_T));
if(ptidsl==NULL)
{
dgprintf(1, "unable to allocate memory for ptidsl\n");
return 1;
}
*ppIHw=ptidsl;
shim_osZeroMemory((char *) ptidsl, sizeof(ITIDSLHW_T));
/* Unreset the ADSL Subsystem */
rc=dslhal_support_unresetDslSubsystem();
if(rc)
{
dgprintf(1, "unable to reset ADSL Subsystem \n");
shim_osFreeMemory((void *) ptidsl, sizeof(ITIDSLHW_T));
return DSLHAL_ERROR_UNRESET_ADSLSS;
}
ptidsl->fwimage = shim_osAllocateVMemory(DSP_FIRMWARE_MALLOC_SIZE);
if(!ptidsl->fwimage)
{
dgprintf(1,"Failed to Allocate Memory for DSP firmware binary \n");
return DSLHAL_ERROR_FIRMWARE_MALLOC;
}
/* read firmware file from flash */
rc=shim_osLoadFWImage(ptidsl->fwimage);
if(rc<0)
{
dgprintf(1, "unable to get fw image\n");
shim_osFreeVMemory((void *)ptidsl->fwimage,DSP_FIRMWARE_MALLOC_SIZE);
shim_osFreeMemory((void *) ptidsl, sizeof(ITIDSLHW_T));
return DSLHAL_ERROR_NO_FIRMWARE_IMAGE;
}
else
{
ptidsl->imagesize = rc;
}
/* Compute the CRC checksum on the image and validate the image */
/* Validate the image in the RAM */
/* load fw to DSP */
if(dslhal_support_hostDspCodeDownload(ptidsl))
{
dgprintf(0,"dsp load error\n");
for(i=0; i<ptidsl->numOlayPages; i++)
{
if(ptidsl->olayDpPage[i].PmemStartWtAddr !=NULL)
{
shim_osFreeDmaMemory((void *) ptidsl->olayDpPage[i].PmemStartWtAddr,
ptidsl->olayDpPage[i].OverlayXferCount);
}
}
for(i=0; i<ptidsl->numProfiles; i++)
{
if(ptidsl->coProfiles[i].PmemStartWtAddr != NULL)
shim_osFreeDmaMemory((void *)ptidsl->coProfiles[i].PmemStartWtAddr, ptidsl->coProfiles[i].OverlayXferCount);
}
if(ptidsl->constDisplay.PmemStartWtAddr != NULL)
shim_osFreeDmaMemory((void *)ptidsl->constDisplay.PmemStartWtAddr, ptidsl->constDisplay.OverlayXferCount);
shim_osFreeVMemory((void *)ptidsl->fwimage,DSP_FIRMWARE_MALLOC_SIZE);
shim_osFreeMemory((void *) ptidsl, sizeof(ITIDSLHW_T));
return DSLHAL_ERROR_CODE_DOWNLOAD;
}
/* set flag to indicated overlay pages are loaded */
ptidsl->bOverlayPageLoaded = 1;
/* set auto retrain to 1 to disble the overlay page reload */
ptidsl->bAutoRetrain = 1;
if (triggerDsp250MHZ)
{
dslhal_support_setDsp250MHzTrigger(ptidsl);
}
/* unreset Raptor */
/* change this to new function */
/* This function should basically bring DSP out of reset bit 23 of PRCR */
/* Function is ready but bypassed for Pre-Silicon */
rc=dslhal_support_unresetDsp();
if (rc)
{
dgprintf(0,"unable to bring DSP out of Reset\n");
for(i=0; i<ptidsl->numOlayPages; i++)
{
if(ptidsl->olayDpPage[i].PmemStartWtAddr !=NULL)
{
shim_osFreeDmaMemory((void *) ptidsl->olayDpPage[i].PmemStartWtAddr,
ptidsl->olayDpPage[i].OverlayXferCount);
}
}
for(i=0; i<ptidsl->numProfiles; i++)
{
if(ptidsl->coProfiles[i].PmemStartWtAddr != NULL)
shim_osFreeDmaMemory((void *)ptidsl->coProfiles[i].PmemStartWtAddr, ptidsl->coProfiles[i].OverlayXferCount);
}
if(ptidsl->constDisplay.PmemStartWtAddr != NULL)
shim_osFreeDmaMemory((void *)ptidsl->constDisplay.PmemStartWtAddr, ptidsl->constDisplay.OverlayXferCount);
shim_osFreeVMemory((void *)ptidsl->fwimage,DSP_FIRMWARE_MALLOC_SIZE);
shim_osFreeMemory((void *) ptidsl, sizeof(ITIDSLHW_T));
return DSLHAL_ERROR_UNRESET_DSP;
}
shim_osFreeVMemory((void *)ptidsl->fwimage,DSP_FIRMWARE_MALLOC_SIZE);
dgprintf(4,"dslhal_api_dslStartup() done\n");
/* Add the code to initialize the host interface variables */
ptidsl->AppData.useBitField = FALSE;
/* Add code to tickle the host interface */
return DSLHAL_ERROR_NO_ERRORS;
}
/******************************************************************************************
* FUNCTION NAME: dslhal_api_dslShutdown
*
*******************************************************************************************
* DESCRIPTION: routine to shutdown ax5 modem and free the resource
*
* INPUT: tidsl_t *ptidsl
*
* RETURN: NULL
*
*
*****************************************************************************************/
int dslhal_api_dslShutdown(tidsl_t *ptidsl)
{
int rc= DSLHAL_ERROR_NO_ERRORS;
int i;
dgprintf(5, "dslhal_api_dslShutdown\n");
rc = dslhal_support_writeHostMailbox(ptidsl, HOST_DSLSS_SHUTDOWN, 0, 0, 0);
if(rc)
{
dgprintf(1, " unable to reset DSP \n");
rc = DSLHAL_ERROR_RESET_DSP;
}
/* DSP need 50 ms to send out the message*/
shim_osClockWait(60 * 1000);
rc = dslhal_support_writeHostMailbox(ptidsl, HOST_DGASP, 0, 0, 0);
/* free memory allocated*/
for(i=0; i<ptidsl->numOlayPages; i++)
{
if(ptidsl->olayDpPage[i].PmemStartWtAddr !=NULL)
{
shim_osFreeDmaMemory((void *) ptidsl->olayDpPage[i].PmemStartWtAddr,
ptidsl->olayDpPage[i].OverlayXferCount);
}
}
for(i=0; i<ptidsl->numProfiles; i++)
{
if(ptidsl->coProfiles[i].PmemStartWtAddr != NULL)
shim_osFreeDmaMemory((void *)ptidsl->coProfiles[i].PmemStartWtAddr, ptidsl->coProfiles[i].OverlayXferCount);
}
if(ptidsl->constDisplay.PmemStartWtAddr != NULL)
shim_osFreeDmaMemory((void *)ptidsl->constDisplay.PmemStartWtAddr, ptidsl->constDisplay.OverlayXferCount);
shim_osFreeMemory((void *)ptidsl, sizeof(tidsl_t));
rc = dslhal_support_resetDsp();
if(rc)
{
dgprintf(1, " unable to reset ADSL subsystem \n");
rc = DSLHAL_ERROR_RESET_DSP;
}
rc = dslhal_support_resetDslSubsystem();
if(rc)
{
dgprintf(1, " unable to reset ADSL subsystem \n");
rc = DSLHAL_ERROR_RESET_ADSLSS;
}
return rc;
}
/******************************************************************************************
* FUNCTION NAME: dslhal_api_getDslHalVersion
*
*******************************************************************************************
* DESCRIPTION: This routine supply DSL Driver version.
*
* INPUT: tidsl_t * ptidsl
* void *pVer, DSP Driver Version Pointer
*
* RETURN: 0 --succeeded
* 1 --Failed
* Note: See verdef_u.h for version structure definition.
*****************************************************************************************/
void dslhal_api_getDslHalVersion(void *pVer)
{
dslVer *pVersion;
pVersion = (dslVer *)pVer;
pVersion->major = (unsigned char) DSLHAL_VERSION_MAJOR;
pVersion->minor = (unsigned char) DSLHAL_VERSION_MINOR;
pVersion->bugfix = (unsigned char) DSLHAL_VERSION_BUGFIX;
pVersion->buildNum = (unsigned char) DSLHAL_VERSION_BUILDNUM;
pVersion->timeStamp = (unsigned char) DSLHAL_VERSION_TIMESTAMP;
}
/********************************************************************************************
* FUNCTION NAME: dslhal_api_processMailBox()
*
*********************************************************************************************
* DESCRIPTION: Common routine only used in dslhal_api_handleTrainingInterrupt()
* and dslhal_api_pollTrainingStatus()
* Input: tidsl_t *ptidsl
* DEV_HOST_dspOamSharedInterface_t *p_dspOamSharedInterface
* intFlag : 0: polling, 1: interrupt
*
* Return: modem status
* -1 failed
*
********************************************************************************************/
#if 1 //cph
static int dslhal_api_processMailBox(tidsl_t *ptidsl,
DEV_HOST_dspOamSharedInterface_t *p_dspOamSharedInterface, int intFlag)
{
int cmd;
int tag;
int parm1,parm2;
#ifdef EFM_DEBUG
extern unsigned int g_efm_proc_ctl;
#endif
// unsigned int msg1;
// unsigned int msg2;
int rc;
unsigned int failState;
static unsigned int GhsIndex=0;
dgprintf(4,"dslhal_api_processMailBox\n");
while (dslhal_support_readDspMailbox(ptidsl,&cmd, &tag, &parm1, &parm2) == DSLHAL_ERROR_NO_ERRORS )
{
dgprintf(4,"mailbox message: 0x%x\n", cmd);
switch (cmd) {
case DSP_IDLE:
{
dgprintf(4,"DSP_IDLE\n");
ptidsl->lConnected=0;
ptidsl->AppData.bState=0;
hybrid_selected=888;
if ((intFlag == 0) // if polling(intFlag=0), put some delay
&& (ptidsl->bAutoRetrain == 0) )
{
while(ptidsl->bOverlayPageLoaded == 0)
shim_osClockWait(6400);
}
if(showtimeFlag == TRUE)
{
dslhal_api_resetTrainFailureLog(ptidsl);
dslhal_support_advancedIdleProcessing(ptidsl);
showtimeFlag = FALSE;
}
failState = (unsigned int)parm1;
if(failState!=0)
{
ptidsl->AppData.trainFailStates[ptidsl->AppData.trainFails]=failState;
ptidsl->AppData.trainFails++;
if(ptidsl->AppData.trainFails >= 30)
ptidsl->AppData.trainFails=0;
}
for(GhsIndex=0;GhsIndex<10;GhsIndex++)
{
for(rc=0;rc<62;rc++)
ptidsl->AppData.dsl_ghsRxBuf[GhsIndex][rc]=0;
}
GhsIndex=0;
/* add code for reload overlay pages */
if(ptidsl->bAutoRetrain == 0 && ptidsl->bOverlayPageLoaded == 0)
{
dslhal_support_restoreTrainingInfo(ptidsl);
ptidsl->bOverlayPageLoaded = 1;
}
/* command DSP to ACTREQ */
rc = dslhal_support_writeHostMailbox(ptidsl, HOST_ACTREQ, 0, 0, 0);
if (rc)
return DSLHAL_ERROR_MAILBOX_WRITE;
break;
}
case DSP_ATM_TC_SYNC:
{
dgprintf(4,"\nDSP_ATM_TC_SYNC\n");
showtimeFlag = TRUE;
ptidsl->lConnected=1;
if(ptidsl->bAutoRetrain == 0 && ptidsl->bOverlayPageLoaded == 1)
{
dslhal_support_clearTrainingInfo(ptidsl);
ptidsl->bOverlayPageLoaded = 0;
}
break;
}
case DSP_ACTIVE:
{
if (intFlag) // if interrupt (intFlag=1)
ptidsl->AppData.showtimeCount ++;
else // polling (intFlag=0)
ptidsl->lConnected=0;
ptidsl->AppData.bState = RSTATE_SHOWTIME;
dgprintf(4,"DSP_ACTIVE");
//
// The dslhal_support_getMaxUsTones()
// below will also call dslhal_support_getTrainedMode(), and read
// TrainedMode, annex_selected & psd_mask_qualifier.
//
ptidsl->AppData.max_us_tones = dslhal_support_getMaxUsTones(ptidsl);
ptidsl->AppData.max_ds_tones = (ptidsl->AppData.TrainedMode & ADSL2PLUS_MASKS) ? 512: 256; //dslhal_support_getMaxDsTones(ptidsl);
#if 1 // LOF CQ10226
// clean the LOF and LPR flags/counters.
ptidsl->AppData.LOF_f = 0;
ptidsl->AppData.LOF_errors = 0;
ptidsl->AppData.coLOF_f = 0;
ptidsl->AppData.coLofErrors = 0;
ptidsl->AppData.LPR = 0; // clear Loss-of-Power primitive
#endif
break;
}
case DSP_ATM_NO_TC_SYNC:
{
dgprintf(4,"\nDSP_ATM_TC_NOSYNC\n");
ptidsl->lConnected=0;
/* add code for reload overlay pages */
break;
}
case DSP_OVERLAY_START:
{
dgprintf(2,"DSP_OVERLAY_START: %d \n",tag);
break;
}
case DSP_OVERLAY_END:
{
dgprintf(2,"DSP_OVERLAY_END: %d \n",tag);
rc = dslhal_support_checkOverlayPage(ptidsl,tag);
if(rc == DSLHAL_ERROR_OVERLAY_CORRUPTED)
{
dgprintf(0,"Overlay Page: %d CORRUPTED \n",tag);
return(0-DSLHAL_ERROR_OVERLAY_CORRUPTED);
}
break;
}
case DSP_HYBRID:
{
dgprintf(2,"DSP_HYBRID (Hybrid Metrics Avail)\n");
hybrid_selected = tag;
break;
}
case DSP_XMITBITSWAP:
{
dgprintf(4,"DSP_XMITBITSWAP\n");
rc = dslhal_support_aocBitSwapProcessing(ptidsl,0);
break;
}
case DSP_RCVBITSWAP:
{
dgprintf(4, "DSP_RCVBITSWAP\n");
rc = dslhal_support_aocBitSwapProcessing(ptidsl,1);
break;
}
case DSP_GHSMSG:
{
dgprintf(3,"DSP_GHSMSG: Rcvd bytes: %d \n",tag);
dgprintf(3,"Addr: 0x%x\n", p_dspOamSharedInterface->ghsDspRxBuf_p);
if(GhsIndex > 9)
GhsIndex=0;
rc = dslhal_support_blockRead(
(void *)dslhal_support_byteSwap32((unsigned int)p_dspOamSharedInterface->ghsDspRxBuf_p),
&ptidsl->AppData.dsl_ghsRxBuf[GhsIndex++][0], tag);
break;
}
case DSP_CRATES1:
{
dgprintf(3,"DSP_CRATES1: (C-Rates1 Ready)\n");
rc = dslhal_support_gatherRateMessages(ptidsl);
break;
}
case DSP_SNR:
{
dgprintf(3,"DSP_SNR: SNR Data Ready\n");
rc = dslhal_support_gatherSnrPerBin(ptidsl,tag);
break;
}
case DSP_EOC:
{
dgprintf(3,"DSP_EOC message:tag=%02x, cmd1=%02x, cmd2=%02x (%s%02x)\n", tag, parm1, parm2,
(parm1 & 0x04) ? "Reg" : "Data",
((parm1>>5)|(parm2<<3))&0xFF);
rc = dslhal_support_gatherEocMessages(ptidsl,tag,parm1,parm2);
break;
}
case DSP_TRAINING_MSGS:
{
dgprintf(3,"DSP_TRAINING_MSGSi \n");
rc = dslhal_support_gatherAdsl2Messages(ptidsl,tag,parm1,parm2);
break;
}
case DSP_CLEAR_EOC:
{
dgprintf(2, "DSP_CLEAR_EOC:tag=%02x, cmd1=%02x, cmd2=%02x\n", tag, parm1, parm2);
ptidsl->AppData.clear_eoc = 1;
break;
}
//UR8_MERGE_START CQ11446
//Added handling of BROWNOUT message for dying gasp
case DSP_DGASP:
{
//#define REG_SWRCR (PRCR_BASE + 0x0004)
//#define SWRCR_SWR0 0x00000001
// DSLHAL_REG32(REG_SWRCR) |= SWRCR_SWR0;
dgprintf(5,"\nDSP_GASP!!! %d\n", tag);
ptidsl->AppData.LPR = 1;
break;
}
case DSP_BROWNOUT:
{
//#define REG_SWRCR (PRCR_BASE + 0x0004)
//#define SWRCR_SWR0 0x00000001
// DSLHAL_REG32(REG_SWRCR) |= SWRCR_SWR0;
dgprintf(5,"\nBROWN_OUT!!! %d\n", tag);
ptidsl->AppData.LPR = 1;
break;
}
//UR8_MERGE_END CQ11446
#if 1 // LOF CQ10226
case DSP_LOF:
{
dgprintf(0,"\nDSP_LOF!!! tag=%02x, cmd1=%02x, cmd2=%02x\n", tag, parm1, parm2);
if (parm1 == 0)
{
ptidsl->AppData.LOF_f = parm2;
ptidsl->AppData.LOF_errors += parm2;
}
else
{
ptidsl->AppData.coLOF_f = parm2;
ptidsl->AppData.coLofErrors += parm2;
}
break;
}
#endif
//UR8_MERGE_START CQ10442 Manjula K
case DSP_SRA:
{
dgprintf(0,"\nDSP_SRA!!! tag=%02x, cmd1=%02x, cmd2=%02x\n", tag, parm1, parm2);
ptidsl->AppData.DSConRate = (parm2<<8) | parm1;
ptidsl->AppData.SRA = 1;
break;
}
//UR8_MERGE_END CQ10442
#ifdef AR7_EFM
//UR8_MERGE_START CQ11466
case DSP_GHS_TCMODE:
{
#ifdef EFM_DEBUG
// toggle mode for auto-switch testing...
if (g_efm_proc_ctl & 8)
{
if (ptidsl->ghs_TCmode==0)
ptidsl->ghs_TCmode = parm1;
else
{
if (ptidsl->ghs_TCmode== TC_MODE_ATM) // hack hack!!
parm1 = TC_MODE_PTM; // override
else
parm1 = TC_MODE_ATM;
}
}
#endif
ptidsl->ghs_TCmode = parm1;
ptidsl->configFlag |= CONFIG_FLAG_TC; // indicate TC Mode set
break;
}
//UR8_MERGE_END CQ10442
#endif
default:
{
dgprintf(0,"DSP_Unknown? 0x%x\n", cmd);
break;
}
}; // switch
} // while
#if 0 //cph999
dslhal_support_readTextMailbox(ptidsl,&msg1, &msg2);
dgprintf(5,"Text Message Part1: 0x%x \t Text Message Part2: 0x%x \n",msg1,msg2);
#endif
return DSLHAL_ERROR_NO_ERRORS;
}
#endif
/********************************************************************************************
* FUNCTION NAME: dslhal_api_pollTrainingStatus()
*