This repo contains the VHDL Programs that I have completed in my M.Sc SEM-III using Xilinx ISE Design Suite
- A 4 bit adder with structural model
- Full adder with structural model
- Full adder with behavioural model
- Ripple carry adder
- A 4 bit subtractor
- Full subtractor
- A 4 bit multiplier
- A 4x4 bit multiplier
- Comprator 3 bit
- 4 Bit up counter with reset
- 16 bit up counter with reset
- Alternate Up/Down counter with reset
- 4 Bit down counter
Each program has been written in file with .v extension. For example "1. Adder_4_Bit_Structural_Model" requires the following:
Adder_1_Bit.v // simple 1 bit adder file
Adder_4_Bit.v // 4 bit adder file that uses the 1 bit adders as a unit
Adder_4_Bit_Testbench.v //Testbench file used to define possible cases to test the program against that