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RV32I 5-Stage Pipelined CPU

Description

This repository builds upon the work of RV32I_Single_Cycle_CPU by extending the RISC-V Data Path to support a 5-Stage Pipelined CPU architecture. It simplifies the RV32I Single Cycle CPU and enhances it into a more efficient pipelined design.

Pre-Requisites

  • Venus Simulator
  • EmulsiV Simulator
  • Logisim Simulator
  • VS Code Integrated Development Environment
  • Vivado Design Suite