CSE-306-Computer-Architecture-Sessional

This is a repository containing all the simulations and reports of CSE-306 Computer Architecture Sessional.

4-bit ALU

• Problem Statement
• Report

This ALU contains:

• Two 4-bit inputs A and B
• Three control signals cs₂, cs₁, cs₀ as ALU opcodes
• One 4-bit output
• Four flags: C (Carry), S (Sign), V (Overflow), Z (Zero)

Implemented functions and opcodes:

Control Signals			Functions
cs2	cs1	cs0
0	0	0	AND
0	0	1	Sub
0	1	X	Decrement A
1	0	0	Complement A
1	0	1	XOR
1	1	X	Add

See detailed truth tables and diagrams from the Report

Block diagram:

Flags:

• Carry (C): Set if there is a carry out of the most significant bit.
• Sign (S): Reflects the highest order bit of the result.
• Overflow (V): Set if there is a signed overflow.
• Zero (Z): Set if the result is zero.

Floating Point Adder

• Problem Statement
• Circuit files
• Report

The adder takes two 32 bit floating point numbers and adds them together. The numbers are represented in the following format:

Sign	Exponent	Fraction
1 bit	12 bits	19 bits (Lowest bits)

The numbers are in normalized form. There are two flags U (underflow) and O (overflow) which are set if the result is too small or too large to be represented in the format.

Flow chart:

Circuit Diagram:

What individual components do:

• Sign check: Checks if a 32 floating point number is positive, negative or the exponent is zero. If the number is positive then the output is the same as input. If the number is negative then it outputs the two's complement of the input. And if the exponent is zero then the output is zero.
• Normalizer: Normalizes a floating point number. But if the number is overflowed or underflowed while trying to normalize then the appropriate flags are set.
• Rounder: Rounds the 32 bit significand to 19 bits.

Note:

• See detailed diagrams from the Report
• There's some correction in the exponent circuit, see README of the FP Adder folder for details.

4-bit MIPS Processor

• Problem Statement
• MIPS Codes and Diagram

Design Specification:

• Address Bus: 8 bits
• Data Bus: 4 bits
• Registers: $zero, $t0, $t1, $t2, $t3, $t4 (all 4-bits)
• Control Unit: Microprogrammed, using Control Words stored in a special memory (EEPROM)

Instruction Set:

• Arithmetic Instructions:
  • add (A): Adds two registers.
  • addi (B): Adds an immediate value to a register.
  • sub (C): Subtracts two registers.
  • subi (D): Subtracts an immediate value from a register.
• Logical Instructions:
  • and (E): Performs bitwise AND on two registers.
  • andi (F): Performs bitwise AND with an immediate value.
  • or (G): Performs bitwise OR on two registers.
  • ori (H): Performs bitwise OR with an immediate value.
  • sll (I): Shifts a register value left by a specified amount.
  • srl (J): Shifts a register value right by a specified amount.
  • nor (K): Performs bitwise NOR on two registers.
• Memory Instructions:
  • lw (L): Loads a word from memory to a register.
  • sw (M): Stores a word from a register to memory.
• Control Instructions:
  • beq (N): Branches if two registers are equal.
  • bneq (O): Branches if two registers are not equal.
  • j (P): Jumps to a specified address.

MIPS Instruction Formats:

• R-type:

Opcode	Src Reg 1	Src Reg 2	Dst Reg
4-bits	4-bits	4-bits	4-bits

• S-type:

Opcode	Src Reg 1	Dst Reg	Shamt
4-bits	4-bits	4-bits	4-bits

• I-type:

Opcode	Src Reg 1	Src Reg 2/Dst Reg	Addr./Immdt.
4-bits	4-bits	4-bits	4-bits

• J-type:

Opcode	Target Jump Address		0
4-bits	8-bits		4-bits

Instruction Set Assignment:

Each group has a specific assignment of instruction opcodes based on their section and group number. Refer to the provided assignment document for detailed opcode assignments.

Additional MIPS Details:

The repository contains additional details and resources related to the 4-bit MIPS processor, including simulation files and implementation guides. You can explore these resources in the Offline 3 - MIPS directory of the repository.

Circuit Diagram: