FPGA UART Protocol

Authors: Bryce Leung, Sahaj Singh

UART Protocol made for Altera DE2-115 FPGA in VHDL

Contents:

• General Design Overview
  • How to Use
• UART Controller
  • Baud Rate Generation
  • Data Framing
  • Error Detetion and Correction
  • Handshaking
• TX
  • TX Testbench
• RX
  • RX Testbench

FPGA UART Protocol Documentation:

General Design Overview

The UART system is designed with the following subsystems:

• Baud Rate Generation
• Data Framing
• Error Detection and Correction
• Handshaking

These subsystems work together to enable synchronous data transmission between UART devices.

How to Use

Steps to prepare the FPGA UART Module:

1. Clone this repository to your local machine.
2. Ensure that you have the necessary FPGA development tools installed.
3. Open the project with your preferred FPGA development environment.
4. Run the provided testbenches to verify the functionality of the UART protocol.
5. Synthesize the design and program your FPGA board with the generated bitstream.

Operating the Module:

• To use the UART Module use the onboard switches 0 to 7 and then press Key 0 to transmit the data.
• To set the BAUD Rate use the onboard switches 0 to 17 and then press Key 1 to set the baud rate.
• To reset the module simply press Key 3.

UART Controller

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The UART controller is the central component of the system, managing the communication between the transmitter and receiver modules. The controller uses a state machine to handle the different stages of data transmission and reception.

Baud Rate Generation

The baud rate generation subsystem is responsible for synchronizing the transmitter and receiver modules. It calculates the number of clock cycles required to send one bit of data and ensures that both devices operate at the same baud rate.

Data Framing

The data framing subsystem adds start and stop bits to each data byte for synchronization purposes. It also adds a parity bit for error detection and correction.

Error Detection and Correction

The error detection and correction subsystem uses parity checking to ensure the integrity of the transmitted data. If an error is detected, the system can perform error correction or request retransmission of the data.

Handshaking

The handshaking subsystem controls the flow of data between devices.

TX

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The transmitter module is responsible for sending data serially to the receiver. It includes the following components:

• Data framing
• Baud rate generation
• Handshaking

TX Testbench

The TX testbench verifies the functionality of the transmitter module. It simulates various scenarios, including different data patterns, baud rates, and handshaking methods.

RX

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RX Testbench

The testbench for the RX component tested different cases of recieving correct and incorrect data.