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Write through LRU 4 Way Set Associative Cache simulation. The objective is to measure the miss rate of this kind of cache.

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Jeremias-V/Cache-Architecture

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include
include
 
 
src
src
 
 
.gitignore
.gitignore
 
 
FillRAM.py
FillRAM.py
 
 
RAM-Data.txt
RAM-Data.txt
 
 
README.md
README.md
 
 
TestInput.txt
TestInput.txt
 
 
TestSustentacion.txt
TestSustentacion.txt
 
 
compile.sh
compile.sh
 
 

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Instructions

  1. Modify RAM-Data.txt contents as desired, the number of lines in that file must be 2048, you can also run python3 FillRam.py to modify the contents with random values.
  2. Compile with gcc -o cache ./src/* or run ./compile.sh while on parent directory.
  3. Run the compiled binary with ./cache.

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Write through LRU 4 Way Set Associative Cache simulation. The objective is to measure the miss rate of this kind of cache.

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c simulation python3 lru-cache ram-data

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