#1121: Fix unittests

JonathanSalwan · Apr 19, 2022 · a245cd0 · a245cd0
1 parent 37e2756
commit a245cd0
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Showing 3 changed files with 21 additions and 13 deletions.
diff --git a/src/libtriton/arch/irBuilder.cpp b/src/libtriton/arch/irBuilder.cpp
@@ -108,7 +108,8 @@ namespace triton {
         if (this->buildSemantics(inst) == false) {
           return false;
         }
-        if (inst.isControlFlow() && --count) {
+        count--;
+        if (inst.isControlFlow() && count) {
           throw triton::exceptions::IrBuilder("IrBuilder::buildSemantics(): Do not add instructions in a block after a branch instruction.");
         }
       }

diff --git a/src/libtriton/bindings/python/objects/pyBasicBlock.cpp b/src/libtriton/bindings/python/objects/pyBasicBlock.cpp
@@ -15,6 +15,13 @@
 #include <iostream>
 
 
+/* setup doctest context
+
+>>> from __future__ import print_function
+>>> from triton import *
+>>> ctx = TritonContext(ARCH.X86_64)
+
+*/
 
 /*! \page py_BasicBlock_page BasicBlock
     \brief [**python api**] All information about the BasicBlock Python object.

diff --git a/src/testers/unittests/test_disass.py b/src/testers/unittests/test_disass.py
@@ -297,12 +297,12 @@ def test_inst3(self):
         ]
         raw = b"".join(code)
         self.ctx.setConcreteMemoryAreaValue(0x1000, raw)
-        insts = self.ctx.disassembly(0x1000)
-        self.assertEqual(str(insts), '[0x1000: movabs rcx, 0x1122334455667788, '
-                                      '0x100a: inc rcx, '
-                                      '0x100d: mov rax, rcx, '
-                                      '0x1010: leave, '
-                                      '0x1011: ret]')
+        block = self.ctx.disassembly(0x1000)
+        self.assertEqual(str(block.getInstructions()), '[0x1000: movabs rcx, 0x1122334455667788, '
+                                                       '0x100a: inc rcx, '
+                                                       '0x100d: mov rax, rcx, '
+                                                       '0x1010: leave, '
+                                                       '0x1011: ret]')
 
     def test_inst4(self):
         code = [
@@ -315,12 +315,12 @@ def test_inst4(self):
         ]
         raw = b"".join(code)
         self.ctx.setConcreteMemoryAreaValue(0x1000, raw)
-        insts = self.ctx.disassembly(0x1000)
-        self.assertEqual(str(insts), '[0x1000: movabs rcx, 0x1122334455667788, '
-                                      '0x100a: inc rcx, '
-                                      '0x100d: mov rax, rcx, '
-                                      '0x1010: leave, '
-                                      '0x1011: jmp rax]')
+        block = self.ctx.disassembly(0x1000)
+        self.assertEqual(str(block.getInstructions()), '[0x1000: movabs rcx, 0x1122334455667788, '
+                                                       '0x100a: inc rcx, '
+                                                       '0x100d: mov rax, rcx, '
+                                                       '0x1010: leave, '
+                                                       '0x1011: jmp rax]')
 
     def test_inst5(self):
         code = [