Designing and verifying a system in a bank using Verilog to monitor the client queue in front of tellers , the system is called BBqM.
Implementing an embedded system inside a bank which monitors the clients queue in front of the tellers. Monitoring was divided into calculating number of people waiting in the queue, and displaying the expected waiting time for each client in the queue, and the maximum number of clients in the queue. The system was simulated using ModelSim, and coded using Verilog. https://github.com/Manar20575/Architecture-Project
In this project, you are going to model the operation of BBqMTM in C Language. Then translate some parts to MIPS assembly language and verify it via simulation utilizing Single-Cycle MIPS processor
Manar Hamada, Menna Omran, and Mona Hamdy