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The EDSAC computer had over thirty delay lines. The hardware peripheral air delay line shall be simulating the 72 bit accumulator since it is one of smaller lines. This air delay line will send the 72 bits in 2 seconds due to the length of the tube which is small due to strength of the microphone.

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Calculations:

• The velocity of sound through air is 343m/s.
• If distance is 1m, total delay is 1/343 = 0.002915452s = 2.92ms.
• Delay per bit is 2.92*10^-3/72 = 0.000040492s = 40.5us = 1/24696 = 1/(24.7kHz)
• Frequency is 343/(1/72) = 343*72 = 24696 = 24.7kHz

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The circuit plan is:

• Speaker has a low pass filter
• Microphone is amplified with lm741 inverter amplifier circuit twice
• Inverter output can go into a half wave rectifier
• Can use a lm339 compatator circuit to make more digital
• Able to get output between 0v and 0.3v
• Needs more amplification
• Use a 3 transistor circuit??

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There are some problems that will be faced:

• Reflections (leave tube open? experiment with the reflections)
• Interfacing (since doing once hardware done may get hardware wrong)
• V. loud