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FPGA optimized structure #53

Merged
merged 85 commits into from
Sep 12, 2022
Merged

FPGA optimized structure #53

merged 85 commits into from
Sep 12, 2022

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MasterPlayer
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Close issue #51

MasterPlayer and others added 30 commits July 3, 2022 22:36
if external signal which connected to output port setupped to zero, after implementation this port optimized
update data to internal register memory (read_memory) always after writing data or calibration process
Interrupt must be highest priority, calibration high priority, requesting data is lowest priority
its deasserted when not readed data from device
For single request setup address and size for perform short requests from device
@MasterPlayer MasterPlayer added hardware process working in hardware software process working in software hardware issue issues in hardware mech software issue issues caused by software problem labels Sep 12, 2022
@MasterPlayer MasterPlayer self-assigned this Sep 12, 2022
@MasterPlayer MasterPlayer merged commit 69b1acc into main Sep 12, 2022
@MasterPlayer MasterPlayer deleted the opt_resource branch September 12, 2022 15:22
This was linked to issues Sep 12, 2022
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Update software processing Optimize FPGA structure
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