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Configuration register space

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Max edited this page Feb 5, 2022 · 21 revisions

This page is description of configuration register space

Configuration needed for control component. It consists of 64 registers, where 16 registers used for control component, and 48 registers realize buffer for holding data from device, which readed from FIFO queue when FIFO interrupt from component ADXL345 asserted.

All registers have width of 32 bit. Access to register realized over AXI-Lite protocol

registers with offsets 0x00-0x3F intended for control device registers with offsets 0x40-0xFF intended for store data from device, which readed from ADXL345 in WATERMARK/OVERRUN interrupt processing.

Configuration register space

OFFSET REGISTER NAME ACCESS DESCRIPTION
0x00 CTL_REG R/W Component control register for enable/disable many functions
0x04 REQUEST_INTERVAL_REG R/W Request interval of data from device value in clock period value
0x08 DATA_WIDTH_REG R Number of bytes in data bus
0x0C READ_VALID_COUNT_REG R Number of readed words from device per second
0x10 WRITE_VALID_COUNT_REG R Number of writed words to device ADXL345 per second
0x14 WRITE_TRANSACTIONS_REG R Number of packets sended to device
0x18 READ_TRANSACTIONS_REG R Number of packets received from device
0x1C CLK_PERIOD_REG R Clock period value for internal calculations
0x20 FIFO_STATUS_REG R Status of fifo mode register
0x24 OPT_REQUEST_INTERVAL_REG R Optimal interval for requests data from device according selected bandwidth speed
0x28 CALIBRATION_COUNT_LIMIT_REG R/W Number for limit calibration requests data from device
0x2C CALIBRATION_TIME_REG R Number of clock periods spend for calibration
0x30 RESERVED N/A Reserved register
0x34 RESERVED N/A Reserved register
0x38 RESERVED N/A Reserved register
0x3C RESERVED N/A Reserved register
OFFSET REGISTER NAME ACCESS BITS[31:24] BITS[23:16] BITS[15: 8] BITS[ 7: 0]
0x40 data_register_0 R DATAY1[0] DATAY0[0] DATAX1[0] DATAX0[0]
0x44 data_register_1 R DATAX1[1] DATAX0[1] DATAZ1[0] DATAZ0[0]
0x48 data_register_2 R DATAZ1[1] DATAZ0[1] DATAY1[1] DATAY0[1]
0x4C data_register_3 R DATAY1[2] DATAY0[2] DATAX1[2] DATAX0[2]
0x50 data_register_4 R DATAX1[3] DATAX0[3] DATAZ1[2] DATAZ0[2]
0x54 data_register_5 R DATAZ1[3] DATAZ0[3] DATAY1[3] DATAY0[3]
0x58 data_register_6 R DATAY1[4] DATAY0[4] DATAX1[4] DATAX0[4]
0x5C data_register_7 R DATAX1[5] DATAX0[5] DATAZ1[4] DATAZ0[4]
0x60 data_register_8 R DATAZ1[5] DATAZ0[5] DATAY1[5] DATAY0[5]
0x64 data_register_9 R DATAY1[6] DATAY0[6] DATAX1[6] DATAX0[6]
0x68 data_register_10 R DATAX1[7] DATAX0[7] DATAZ1[6] DATAZ0[6]
0x6C data_register_11 R DATAZ1[7] DATAZ0[7] DATAY1[7] DATAY0[7]
0x70 data_register_12 R DATAY1[8] DATAY0[8] DATAX1[8] DATAX0[8]
0x74 data_register_13 R DATAX1[9] DATAX0[9] DATAZ1[8] DATAZ0[8]
0x78 data_register_14 R DATAZ1[9] DATAZ0[9] DATAY1[9] DATAY0[9]
0x7C data_register_15 R DATAY1[10] DATAY0[10] DATAX1[10] DATAX0[10]
0x80 data_register_16 R DATAX1[11] DATAX0[11] DATAZ1[10] DATAZ0[10]
0x84 data_register_17 R DATAZ1[11] DATAZ0[11] DATAY1[11] DATAY0[11]
0x88 data_register_18 R DATAY1[12] DATAY0[12] DATAX1[12] DATAX0[12]
0x8C data_register_19 R DATAX1[13] DATAX0[13] DATAZ1[12] DATAZ0[12]
0x90 data_register_20 R DATAZ1[13] DATAZ0[13] DATAY1[13] DATAY0[13]
0x94 data_register_21 R DATAY1[14] DATAY0[14] DATAX1[14] DATAX0[14]
0x98 data_register_22 R DATAX1[15] DATAX0[15] DATAZ1[14] DATAZ0[14]
0x9C data_register_23 R DATAZ1[15] DATAZ0[15] DATAY1[15] DATAY0[15]
0xA0 data_register_24 R DATAY1[16] DATAY0[16] DATAX1[16] DATAX0[16]
0xA4 data_register_25 R DATAX1[17] DATAX0[17] DATAZ1[16] DATAZ0[16]
0xA8 data_register_26 R DATAZ1[17] DATAZ0[17] DATAY1[17] DATAY0[17]
0xAC data_register_27 R DATAY1[18] DATAY0[18] DATAX1[18] DATAX0[18]
0xB0 data_register_28 R DATAX1[19] DATAX0[19] DATAZ1[18] DATAZ0[18]
0xB4 data_register_29 R DATAZ1[19] DATAZ0[19] DATAY1[19] DATAY0[19]
0xB8 data_register_30 R DATAY1[20] DATAY0[20] DATAX1[20] DATAX0[20]
0xBC data_register_31 R DATAX1[21] DATAX0[21] DATAZ1[20] DATAZ0[20]
0xC0 data_register_32 R DATAZ1[21] DATAZ0[21] DATAY1[21] DATAY0[21]
0xC4 data_register_33 R DATAY1[22] DATAY0[22] DATAX1[22] DATAX0[22]
0xC8 data_register_34 R DATAX1[23] DATAX0[23] DATAZ1[22] DATAZ0[22]
0xCC data_register_35 R DATAZ1[23] DATAZ0[23] DATAY1[23] DATAY0[23]
0xD0 data_register_36 R DATAY1[24] DATAY0[24] DATAX1[24] DATAX0[24]
0xD4 data_register_37 R DATAX1[25] DATAX0[25] DATAZ1[24] DATAZ0[24]
0xD8 data_register_38 R DATAZ1[25] DATAZ0[25] DATAY1[25] DATAY0[25]
0xDC data_register_39 R DATAY1[26] DATAY0[26] DATAX1[26] DATAX0[26]
0xE0 data_register_40 R DATAX1[27] DATAX0[27] DATAZ1[26] DATAZ0[26]
0xE4 data_register_41 R DATAZ1[27] DATAZ0[27] DATAY1[27] DATAY0[27]
0xE8 data_register_42 R DATAY1[28] DATAY0[28] DATAX1[28] DATAX0[28]
0xEC data_register_43 R DATAX1[29] DATAX0[29] DATAZ1[28] DATAZ0[28]
0xF0 data_register_44 R DATAZ1[29] DATAZ0[29] DATAY1[29] DATAY0[29]
0xF4 data_register_45 R DATAY1[30] DATAY0[30] DATAX1[30] DATAX0[30]
0xF8 data_register_46 R DATAX1[29] DATAX0[29] DATAZ1[30] DATAZ0[30]
0xFC data_register_47 R DATAZ1[31] DATAZ0[31] DATAY1[31] DATAY0[31]

1. CTL_REG (offset 0x00)

Control register enable/disable requests, interrupts, change I2C address of device, reset device, perform calibration, acknowledge for interrupts Offset address is 0x00.

1.1. Fields

Field name Bits Mask Access Description
RESET_LOGIC [0] 0x00000001 R/W Perform reset this component internal logic, disable all requests of data, reset device register space, reset values address, request_interval to default value. Self-cleared after RESET_DURATION interval, no user intervention for deassert this bit.
REQUEST_ENABLE [1] 0x00000002 R/W Enable request data from device with REQUEST_INTERVAL intervals.
IRQ_ALLOW [2] 0x00000004 R/W Allows interrupt processing in component and allow interrupt signal generating to processor
SINGLE_REQUEST [3] 0x00000008 R/W Perform single request data from device. Completion of this operation in CTL_REG[6] bit. Self-cleared, no user intervention for deassert this signal
INTR_ACK [4] 0x00000010 R/W Interrupt ACK from processor deassert ADXL_IRQ signal from component to processor. When interrupt processed on processor, processor deassert ADXL_IRQ signal over writing this bit is 1.
CALIBRATION [5] 0x00000020 R/W Run calibration process in component. Read this bit show status of interrupt. 0 - Calibration complete, 1 - Calibration in progress. Self cleared after calibration was completed, no user intervention for deassert this bit.
SINGLE_REQUEST_PERFORMED [6] 0x00000400 RO Status bit for signalize about single_request perform. if asserted, then single request completely performed, if 0 then single request in progress. Writing this bit has no effect
ON_WORK [7] 0x00000800 RO If asserted, then internal logic perform some work, such as processing interrupts, requesting data or perform single requests, perform calibration. Writing this bit has no effect
I2C_ADDRESS [14:8] 0x00007F00 R/W Address of device I2C without R/W bit. With this address component perform all transactions Read or Write to device
LINK_ON [15] 0x00008000 RO Link with device. Asserts if DEVICE_ID readed successfully and device register[0] = 0xE5. Writing this bit has no effect
VERSION_MINOR [23:16] 0x00FF0000 RO Minor version of component. Writing this bit has no effect
VERSION_MAJOR [31:24] 0xFF000000 RO Major version of component. Writing this bit has no effect

2. REQUEST_INTERVAL_REG (offset 0x04)

This register limits internal clock period counter for perform requests to device ADXL345 with fixed intervals. User can set new request interval of data for any value. Width of this register is 32 bits.

2.1 Equation

Convertation to seconds must be follow for next equation :

RequestIntervalSec = REQUEST_INTERVAL_REG/CLK_PERIOD_REG

3. DATA_WIDTH_REG (offset 0x08)

This register hold information about data width in bits. Needs for calculate data speed, data count and etc. For statistics. Width of this register is 32 bits

4. READ_VALID_COUNT_REG (offset 0x0C)

This register hold value for last 1 second of work component, new data update for 1 second and show how many words received from ADXL345 device. Need for calculate speed in words per second. Width of this register is 32 bit.

4.1 Equation

Speed in bits calculated as follow equation :

DataSpeed = READ_VALID_COUNT_REG/CLOCK_PERIOD*DATA_WIDTH bit/s

5. WRITE_VALID_COUNT_REG (offset 0x10)

This register hold value for last 1 second of work component, new data update for 1 second and show how many words sended from ADXL345. Need for calculate speed in words/second. Width of this register is 32 bit.

5.1 Equation

Speed in bits calculated as follow equation :

DataSpeed = READ_VALID_COUNT_REG/CLOCK_PERIOD*DATA_WIDTH bit/s

6. WRITE_TRANSACTIONS_REG (offset 0x14)

This register hold and store number of packets which sended to ADXL345 device. Needs for collecting statistics. This value read only. Reset statistics counters perform over RESET_LOGIC bit. Writing from AXI interface new data has no effect.

7. READ_TRANSACTIONS_REG (offset 0x18)

This register hold and store number of packets which received from ADXL345 device. Needs for collecting statistics. This value read only. Reset statistics counters perform over RESET_LOGIC bit. Writing from AXI interface new data has no effect.

8. CLK_PERIOD_REG (offset 0x1C)

This register store value of CLK period signal in Hertz and need for calculation internal counters, such as calibration time, speeds, optimal request interval value. Software can read this register for next calculation for statistics. This value read only. Writing from AXI interface new data has no effect.

9. FIFO_STATUS_REG (offset 0x20)

This register hold status.

9.1. Fields

Field name Bits Mask Access Description
ROM_ADDRESS [7:0] 0x000000FF RO current address of ROM memory
OVERRUN [8] 0x00000100 RO current status of FIFO in ADXL345.
RESERVED [31:9] 0xFFFFFE00 N/A reserved fields

10. OPT_REQUEST_INTERVAL (offset 0x24)

Calculated from component optimal request interval according BW_RATE value and CLK_PERIOD.

Equation

Optimal interval calculated as :

OPT_REQUEST_INTERVAL = CLK_PERIOD/BW_RATE

Optimal request interval store value in clock periods.

where BW_RATE is ADXL345 register, CLK_PERIOD - configuration register (offset 0x1C)

11. CALIBRATION_COUNT_LIMIT_REG (offset 0x28)

This register sets number of steps for perform calibration. This value must be power of two. If this value of register is very big, calibration of ADXL345 take long of time, but more accuracy.

12. CALIBRATION_TIME (offset 0x2C)

This register show time in clock periods how long time calibration performed

For convert clock periods to seconds use next equation

CALIB_TIME_IN_SECONDS = CALIBRATION_TIME/CLK_PERIOD;

data_register_0-data_register_15 (offset 0x40-0xFF)

Register store value of DATAX0/DATAX1/DATAY0/DATAY1/DATAZ0/DATAZ1 from ADXL345, readed if OVERRUN interrupt or WATERMARK interrupt asserted and processed in this component. API allow read and decode this data to RAW or Gravity values

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