Yosys 0.45

Yosys 0.44 .. Yosys 0.45

• Various

  • Added cell types help messages.

• New back-ends

  • Added initial NG-Ultra support. ( synth_nanoxplore )

Yosys 0.44

Yosys 0.43 .. Yosys 0.44

• Various

  • Added ENABLE_LTO compile option to enable link time
    optimizations.
  • Build support for Haiku OS.

• New commands and options

  • Added "keep_hierarchy" pass to add attribute with
    same name to modules based on cost.
  • Added options "-noopt","-bloat" and "-check_cost" to
    "test_cell" pass.

• New back-ends

  • Added initial PolarFire support. ( synth_microchip )

Yosys 0.43

Yosys 0.42 .. Yosys 0.43

• Various

  • C++ compiler with C++17 support is required.
  • Support for IO liberty files for verification.
  • Limit padding from shiftadd for "peepopt" pass.

• Verific support

  • Support building Yosys with various Verific library
    configurations. Can be built now without YosysHQ
    specific patch and extension library.

Resources

This is placeholder for build resources otherwise hosted on other places to make availability higher.

https://yosyshq.net/yosys/nogit/YosysVS-Tpl-v2.zip
https://www.zlib.net/fossils/zlib-1.2.11.tar.gz

Yosys 0.42

Yosys 0.41 .. Yosys 0.42

• New commands and options
  • Added "box_derive" pass to derive box modules.
  • Added option "assert-mod-count" to "select" pass.
  • Added option "-header","-push" and "-pop" to "log" pass.
• Intel support
  • Dropped Quartus support in "synth_intel_alm" pass.

Yosys 0.41

Yosys 0.40 .. Yosys 0.41

• New commands and options

  • Added "cellmatch" pass for picking out standard cells automatically.

• Various

  • Extended the experimental incremental JSON API to allow arbitrary
    smtlib subexpressions.
  • Added support for using ABCs library merging when providing multiple
    liberty files.

• Verific support

  • Expose library name as module attribute.

Yosys 0.40

Yosys 0.39 .. Yosys 0.40

• New commands and options

  • Added option "-vhdl2019" to "read" and "verific" pass.

• Various

  • Major documentation overhaul.
  • Added port statistics to "stat" command.
  • Added new formatting features to cxxrtl backend.

• Verific support

  • Added better support for VHDL constants import.
  • Added support for VHDL 2009.

Yosys 0.39

Yosys 0.38 .. Yosys 0.39

• New commands and options

  • Added option "-extra-map" to "synth" pass.
  • Added option "-dont_use" to "dfflibmap" pass.
  • Added option "-href" to "show" command.
  • Added option "-noscopeinfo" to "flatten" pass.
  • Added option "-scopename" to "flatten" pass.

• SystemVerilog

  • Added support for packed multidimensional arrays.

• Various

  • Added "$scopeinfo" cells to preserve information about
    the hierarchy during flattening.
  • Added sequential area output to "stat -liberty".
  • Added ability to record/replay diagnostics in cxxrtl backend.

• Verific support

  • Added attributes to module instantiation.

Yosys 0.38

Yosys 0.37 .. Yosys 0.38

• New commands and options

  • Added option "-tech" to "opt_lut" pass.
  • Added option "-nokeep_prints" to "hierarchy" pass.
  • Added option "-nolower" to "async2sync" and "clk2fflogic" pass.
  • Added option "-lower" to "chformal" pass.

• Various

  • Added $check cell to represent assertions with messages.
  • Allow capturing $print cell output in CXXRTL.
  • Added API to overwrite existing pass from plugin.
  • Follow the XDG Base Directory Specification for storing history files.
  • Without a known top module, derive all deferred modules (hierarchy pass).
  • Detect and error out on combinational loops in write_aiger.

• Verific support

  • Added option "-no-split-complex-ports" to "verific -import".

Yosys 0.37

Yosys 0.36 .. Yosys 0.37

• New commands and options

  • Added option "-nodisplay" to read_verilog.

• SystemVerilog

  • Correct hierarchical path names for structs and unions.

• Various

  • Print hierarchy for failed assertions in "sim" pass.
  • Add "--present-only" option to "yosys-witness" to omit unused signals.
  • Implement a generic record/replay interface for CXXRTL.
  • Improved readability of emitted code with "write_verilog".