A5-1-and-XOR-PRNG-Image-encryption-using-verilog-

Image encryption using A5/1 and (XOR with PRNG) algorithms . I-CHIP22 PS2 solution

Introduction

• Team name - ARcheus
• Team members - Ayush Agarwal (me) , Raghavansh Singla
• Skills : Verilog , Image Processing , Encryption (CyberSec) , Digital Electronics
• Tools : Vivado , Icarus

This repository contains our work on the problem statment for PS2 of I-CHIP 22 , the verilog event of UDYAM , which is the electronics department fest of IIT BHU . We have encrypted an image using 2 different algorithms ( whose details have been split as Design 1 and Design 2 respectively ) . Image encryption is essential for secure transmission of image data over communication lines hence this project is valuable one .

The PS :

Design 1 details :

Bits were generated using a Pseudo Random Number Generator (PRNG) ( Module for the same has been made and uploaded in the repo ) , and then XORed with the bits of the image . This process is the encryption part . For the decryption part we run the PRNG again and again XOR the same bits . This process decrypts the image since XORing the same number 2 times removes its effect on the original data bit .

Actual Image :

Encrypted Image :

Decrypted Image :

Module for PRNG :

Felt important to show hence added the images here , the rest of the code can be referred from the verilog files in this repository . The PRNG can be made by shifting all the values by one bit , and filling the vacant space by xor of combination of few selected bits .

Design 2 details :

The basic idea of XORing remains the same here , expect that the bits to be XORed are generated by the A5/1 algorithm . The details of the algorithm can be found on the following sites :

• https://www.cryptographynotes.com/2019/02/symmetric-stream-a5by1-algorithm-linear-feedback-shift-register.html
• https://youtu.be/LgZAI3DdUA4

The implementation of A5/1 requires 64 bit secret key and 22 bit public key which are given in the PS ( I have made my own version of the algorithm tho , which dosent need the 22 bit public key )

Module for A5/1 Generator :

Initializing the variables :

Majority function code ( yeah , even verilog has functions , got to know after this project ) :

The reset / initialisation conditions :

The A5/1 Bit Generation code :

The Testbench can be referred from the repository files , wouldn't make sense to paste the whole code here , so please refer to the comments for explanation of the code .