Allow kernel to access PLIC

[blitz]

The kernel needs a mapping of the PLIC. We can model this as a memory resource and use our normal resource mapping scheme.

SaxonSoc on ULX3S has the following PLIC:

                interrupt-controller@c00000 {
                        compatible = "sifive,plic-1.0.0\0sifive,fu540-c000-plic";
                        #interrupt-cells = <0x01>;
                        interrupt-controller;
                        interrupts-extended = <0x01 0x0b 0x01 0x09 0x02 0x0b 0x02 0x09>;
                        reg = <0xc00000 0x400000>;
                        riscv,ndev = <0x20>;
                        phandle = <0x03>;
                };

Docs:

• https://sifive.cdn.prismic.io/sifive%2Fdc4980ff-17db-448b-b521-4c7ab26b7488_sifive+u54-mc+manual+v19.08.pdf
• https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc