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16 Open 99 Closed
16 Open 99 Closed
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Issues list

Obtaining module handle based on the full name of the instance
#1080 opened Jun 28, 2024 by mysoreanoop
1
Efficient backtracking from output ports to input ports
#1078 opened Jun 25, 2024 by alaindargelas
1
Is it possible write SMT2 file from UHDM(Bypassing Yosys)?
#1077 opened Jun 12, 2024 by easyformal
1
bindAny should not look in the current instance for HighConn, only parent instance.
#1074 opened Feb 7, 2024 by pieter3d
1
Create a RTL Netlist view
#1037 opened Oct 5, 2023 by alaindargelas
12
[feature suggestion] Save/restore UHDM in-memory
#902 opened Apr 2, 2023 by yurivict
1
Create "standalone" examples
#783 opened Aug 23, 2022 by alaindargelas
1
Consider publishing generated capnp and uhdm_types.h as release artifacts
#498 opened Sep 13, 2021 by MikePopoloski
1
Support a second parser (other than Surelog) enhancement New feature or request
#319 opened Jul 24, 2020 by mithro
24
Generate a class hierarchy diagram for generated models
#207 opened May 7, 2020 by hs-apotell
4
Create SystemVerilog Constraints Model
#185 opened Apr 22, 2020 by alaindargelas
1
Set up Kokoro CI on this repository
#178 opened Apr 15, 2020 by mithro
1
@rkapuscik
1
Run clang-format automatically on everything
#77 opened Jan 15, 2020 by mithro
@hzeller
2
The hand-written classes should have documentation documentation Improvements or additions to documentation
#74 opened Jan 15, 2020 by hzeller
2
Generate dot file enhancement New feature or request
#73 opened Jan 15, 2020 by hzeller
6
Add Sphinx document generation and publish to readthedocs.io
#40 opened Jan 8, 2020 by mithro
2
ProTip! Exclude everything labeled bug with -label:bug.