Converted HFLG_DBG_TRAP to CPU_INHIBIT_DBG_TRAP

lib86cpu/core/breakpoint.cpp

@@ -45,7 +45,7 @@ cpu_check_watchpoints(cpu_t *cpu, addr_t addr, int dr_idx, int type, uint32_t ei
 	bool match = false;
 	int dr7_type = cpu_get_watchpoint_type(cpu, dr_idx);
 	if (type == DR7_TYPE_DATA_W) {
-		if (((dr7_type == DR7_TYPE_DATA_W) || (dr7_type == DR7_TYPE_DATA_RW)) && !(cpu->cpu_ctx.hflags & HFLG_DBG_TRAP)) {
+		if (((dr7_type == DR7_TYPE_DATA_W) || (dr7_type == DR7_TYPE_DATA_RW)) && !(cpu->cpu_flags & CPU_INHIBIT_DBG_TRAP)) {
 			match = true;
 		}
 	}
@@ -54,7 +54,7 @@ cpu_check_watchpoints(cpu_t *cpu, addr_t addr, int dr_idx, int type, uint32_t ei
 			match = true;
 		}
 	}
-	else if ((type == dr7_type) && !(cpu->cpu_ctx.hflags & HFLG_DBG_TRAP)) { // either DR7_TYPE_IO_RW or DR7_TYPE_DATA_RW
+	else if ((type == dr7_type) && !(cpu->cpu_flags & CPU_INHIBIT_DBG_TRAP)) { // either DR7_TYPE_IO_RW or DR7_TYPE_DATA_RW
 		match = true;
 	}
 

lib86cpu/core/emitter/x64/jit.cpp

@@ -679,7 +679,7 @@ lc86_jit::gen_no_link_checks()
 		m_cpu->cpu_flags |= CPU_FORCE_INSERT;
 	}
 
-	if (m_cpu->cpu_ctx.hflags & HFLG_DBG_TRAP) {
+	if (m_cpu->cpu_flags & CPU_INHIBIT_DBG_TRAP) {
 		LD_R32(EAX, CPU_CTX_EIP);
 		gen_raise_exp_inline<true>(0, 0, EXP_DB, EAX);
 		return;

lib86cpu/core/internal.h

@@ -33,7 +33,6 @@ JIT_API void tlb_invalidate_(cpu_ctx_t *cpu_ctx, addr_t addr);
 // HFLG_PE_MODE: real or protected mode
 // HFLG_CR0_EM: em flag of cr0
 // HFLG_TRAMP: used to select the trampoline tc instead of the hook tc
-// HFLG_DBG_TRAP: used to suppress data/io watchpoints (not recorded in the tc flags)
 // HFLG_CR4_OSFXSR: osfxsr flag of cr4
 // HFLG_CR0_TS: ts flag of cr0
 // HFLG_CR0_MP: mp flag of cr0
@@ -45,7 +44,6 @@ JIT_API void tlb_invalidate_(cpu_ctx_t *cpu_ctx, addr_t addr);
 #define PE_MODE_SHIFT       4
 #define CR0_EM_SHIFT        5
 #define TRAMP_SHIFT         6
-#define DBG_TRAP_SHIFT      7
 #define CR4_OSFXSR_SHIFT    9
 #define CR0_TS_SHIFT        10
 #define INHIBIT_INT_SHIFT   14
@@ -59,7 +57,6 @@ JIT_API void tlb_invalidate_(cpu_ctx_t *cpu_ctx, addr_t addr);
 #define HFLG_PE_MODE        (1 << PE_MODE_SHIFT)
 #define HFLG_CR0_EM         (1 << CR0_EM_SHIFT)
 #define HFLG_TRAMP          (1 << TRAMP_SHIFT)
-#define HFLG_DBG_TRAP       (1 << DBG_TRAP_SHIFT)
 #define HFLG_INHIBIT_INT    (1 << INHIBIT_INT_SHIFT)
 #define HFLG_CR0_MP         (1 << CR0_MP_SHIFT)
 #define HFLG_CR0_TS         (1 << CR0_TS_SHIFT)

lib86cpu/core/translate.cpp

@@ -138,7 +138,8 @@ translated_code_t *cpu_raise_exception(cpu_ctx_t *cpu_ctx)
 					eflags_mask |= (IF_MASK | VIF_MASK);
 				}
 				cpu_ctx->regs.eflags &= ~eflags_mask;
-				cpu_ctx->hflags &= ~(HFLG_DBG_TRAP | HFLG_INHIBIT_INT);
+				cpu_ctx->hflags &= ~HFLG_INHIBIT_INT;
+				cpu_ctx->cpu->cpu_flags &= ~CPU_INHIBIT_DBG_TRAP;
 				cpu_ctx->exp_info.old_exp = EXP_INVALID;
 				if (idx == EXP_PF) {
 					cpu_ctx->regs.cr2 = fault_addr;
@@ -380,7 +381,8 @@ translated_code_t *cpu_raise_exception(cpu_ctx_t *cpu_ctx)
 				cpu_ctx->regs.eflags = (eflags & ~(VM_MASK | RF_MASK | NT_MASK | TF_MASK));
 				cpu_ctx->regs.esp = (cpu_ctx->regs.esp & ~stack_mask) | (esp & stack_mask);
 				cpu_ctx->regs.eip = new_eip;
-				cpu_ctx->hflags &= ~(HFLG_DBG_TRAP | HFLG_INHIBIT_INT);
+				cpu_ctx->hflags &= ~HFLG_INHIBIT_INT;
+				cpu_ctx->cpu->cpu_flags &= ~CPU_INHIBIT_DBG_TRAP;
 				cpu_ctx->exp_info.old_exp = EXP_INVALID;
 				if (idx == EXP_PF) {
 					cpu_ctx->regs.cr2 = fault_addr;
@@ -512,7 +514,8 @@ translated_code_t *cpu_raise_exception(cpu_ctx_t *cpu_ctx)
 		cpu_ctx->regs.eip = vec_entry & 0xFFFF;
 	}
 
-	cpu_ctx->hflags &= ~(HFLG_DBG_TRAP | HFLG_INHIBIT_INT);
+	cpu_ctx->hflags &= ~HFLG_INHIBIT_INT;
+	cpu_ctx->cpu->cpu_flags &= ~CPU_INHIBIT_DBG_TRAP;
 	cpu_ctx->exp_info.old_exp = EXP_INVALID;
 	if (idx == EXP_DB) {
 		cpu_ctx->regs.dr[7] &= ~DR7_GD_MASK;
@@ -1890,7 +1893,7 @@ tc_run_code(cpu_ctx_t *cpu_ctx, translated_code_t *tc)
 		switch (type)
 		{
 		case host_exp_t::pf_exp: {
-			// page fault while excecuting the translated code
+			// page fault while executing the translated code
 			retry_exp:
 			try {
 				// the exception handler always returns nullptr
@@ -1907,12 +1910,11 @@ tc_run_code(cpu_ctx_t *cpu_ctx, translated_code_t *tc)
 
 		case host_exp_t::db_exp: {
 			// debug exception trap (mem/io r/w watch) while executing the translated code.
-			// We set CPU_DBG_TRAP, so that we can execute the trapped instruction without triggering again a de exp,
+			// We set CPU_INHIBIT_DBG_TRAP, so that we can execute the trapped instruction without triggering again a de exp,
 			// and then jump to the debug handler. Note that eip points to the trapped instr, so we can execute it.
 			assert(cpu_ctx->exp_info.exp_data.idx == EXP_DB);
 
-			cpu_ctx->cpu->cpu_flags |= CPU_DISAS_ONE;
-			cpu_ctx->hflags |= HFLG_DBG_TRAP;
+			cpu_ctx->cpu->cpu_flags |= (CPU_DISAS_ONE | CPU_INHIBIT_DBG_TRAP);
 			cpu_ctx->regs.eip = cpu_ctx->exp_info.exp_data.eip;
 			// run the main loop only once, since we only execute the trapped instr
 			int i = 0;

lib86cpu/interface.cpp

@@ -205,7 +205,7 @@ static void cpu_sync_state(cpu_t *cpu)
 		}
 	}
 
-	// there's no need to sync HFLG_TRAMP and HFLG_DBG_TRAP since those can never be set when this is called either from the client or from cpu_run
+	// there's no need to sync HFLG_TRAMP since those can never be set when this is called either from the client or from cpu_run
 	cpu->cpu_ctx.hflags = 0;
 	cpu->cpu_ctx.hflags |= (cpu->cpu_ctx.regs.cs & HFLG_CPL);
 	if (cpu->cpu_ctx.regs.cs_hidden.flags & SEG_HIDDEN_DB) {

lib86cpu/support.h

@@ -12,6 +12,7 @@
 
 // these flags are ORed with the flags in lib86cpu.h, so avoid conflicts
 #define CPU_TIMEOUT             (1 << 3)
+#define CPU_INHIBIT_DBG_TRAP    (1 << 4)
 #define CPU_DISAS_ONE           (1 << 7)
 #define CPU_ALLOW_CODE_WRITE    (1 << 8)
 #define CPU_FORCE_INSERT        (1 << 9)