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Tested and running with latest UMM IRAM heap changes
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Ran sanity tests successfully on 23LC1024 128K SRAM.  Adjusted defines
to ensure UMM knows about our heap.
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@earlephilhower
earlephilhower committed Jan 9, 2021
1 parent e1d580e commit 5bb31a0
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@mhightower83
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Arduino/cores/esp8266/core_esp8266_vm.cpp

Lines 304 to 313 in 5bb31a0

"rsr %0, EXCVADDR;" // read out the faulting address
"movi a4, ~3;" // prepare a mask for the EPC
"and a4, a4, %2;" // apply mask for 32bit aligned base
"l32i a5, a4, 0;" // load part 1
"l32i a6, a4, 4;" // load part 2
"ssa8l %2;" // set up shift register for src op
"src %1, a6, a5;" // right shift to get faulting instruction
:"=r"(excvaddr), "=r"(insn)
:"r"(epc1)
:"a4", "a5", "a6"

Without an & on output spec, "=r"(excvaddr), the register holding input, "r"(epc1), may be reassigned before use. I have seen this with other code that uses this sequence. I am working from memory here it has been a while.

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