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"Phase Locked" Waveform: fix significant jitter, that stresses servos and is clearly audible in Tone output #7022

Merged
merged 153 commits into from
Nov 19, 2020
Merged

"Phase Locked" Waveform: fix significant jitter, that stresses servos and is clearly audible in Tone output #7022

merged 153 commits into from
Nov 19, 2020

Commits on Nov 14, 2020

  1. Allow 100% high or low periods. 

    Let output remain at current level on stopping instead of always turning to low.
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  2. Fix serious jitter issues in previous versions.

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  3. Use ESP.getCycleCount() just like everyone else.

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  4. Highest timer rate at which this runs stable appears to be 2µs (500kHz).

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  5. Guard for zero period length undefined waveforms. 

    Fix for zero duty or off cycles and expiring from them.
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  6. Cycle precision for expiry instead of special treatment for 0 value.

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  7. Give expiry proper precedence over updating a waveform

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  8. Important comment

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  9. Refactored, identical behavior.

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  10. Use plural for bit arrays.

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  11. Fix for completely duty or all off cycle period case.

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  12. Expiration is explicitly relative to service time.

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  13. Comment updated, here it's about cycles not usecs.

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  14. Revert misconception of how waveformToEnable/Disable communicates wit… 

    …h the NMI handler.
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  15. Rewrite to keep phase in sync if period remains same during duty cycl… 

    …e change.

Refactor identifies to distinguish CPU clock cycle from waveform cycle.
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  16. Rather iterate even if full-duty or no-duty cycle in period, than too… 

    … many calculations in NMI handler.
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  17. Must fire timer early to reach waveform deadlines, otherwise under so… 

    …me load aggressive jitter occurs.
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  18. Schedule expiry explicitly, too. 

    Needed to keep track of next timer ccy in each iteration, not just when changing level.
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  19. Quick change lets analogWrite keep phase for any duty cycle (includin… 

    …g 0% and 100%).
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  20. Set duration to multiple of period, so tone stops on LOW pin output.

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  21. Improve phase timing

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  22. Eror causing next Timer IRQ to fail busy-to-off cycle transitions.

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  23. Regression fix, don't reset timer if pending shortly.

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  24. Rather reschedule ISR instead of busy looping during permitted maximu… 

    …m time.
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  25. Lead time improved for ISR

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  26. Reduce number of cycle calculations.

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  27. Reactive the gcc optimize pragmas.

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  28. Simplify calculation.

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  29. handles overshoot where an updated period is shorter than the previou… 

    …s duty cycle
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  30. Misleading code, there must ever be only one bit set at a time, start… 

    … and stop block until the ISR has handled and reset the token.
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  31. Prevent missing a duty cycle unless it is overshot already.

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  32. Continuously remove distant pending waveform edges from the loop, con… 

    …tinuously update now.
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  33. Replace volatile for one-way exchange into ISR with memory fence.

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  34. Remove redundant stack object.

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  35. Revert pending waveform removal from loop - corrupts continuous next … 

    …event computation.
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  36. Reduce if/do ... while to while

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  37. Convert relative timings to absolute.

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  38. Relax waveform start to possibly cluster phases into same IRQ interval.

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  39. max 12us in ISR seems to work best for servo/fan/led/tone combo test.

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  40. Restructured code in ISR for expiration, this saves 36 byte IRAM, and… 

    … improves PWM resolution.
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  41. Simplified overshot detection and 0% / 100% duty cycle.

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  42. Leave ISR early if rescheduling is more promising than busy-waiting u… 

    …ntil next edge.
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  43. Stabilized timings.

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  44. Prevent WDT under load.

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  45. Use clock cycle resolution instead of us for analogWrite.

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  46. Reduce idle calculations in ISR.

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  47. Optimize in-ISR time.

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  48. Support starting new waveform in phase with another running waveform.

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  49. Align phase for analogWrite PWMs.

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  50. Tune preshoot, add lost period fast forward.

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  51. Adapt phase sync code from analogWrite to Servo

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  52. Fix for going off 100% duty cycle period.

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  53. Eschew obfuscation.

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  54. Fixed logic for zero duty cycle.

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  55. Determine generator quantum during same IRQ - this is better than tim… 

    …er resolution, but non-zero.
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  56. Tune timings, fix write barriers and overshoot logic.

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  57. Migrate Tone to waveform with CPU cycle precision

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  58. Can do 60kHz PWM.

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  59. Recalibrated timings after performance optimizations. 

    Initialize GPIO if needed.
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  60. Fix regression for waveform runtime.

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  61. Test cycle duration values for signed arithmetic safety.

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  62. Performance tuning.

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  63. Performance tweak, in-ISR quantum is now 1.12µs.

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  64. Round up duration instead of down - possibly to zero, which means for… 

    …ever.
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  65. Extend phase alignment with optional phase offset.

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  66. Slightly better in-ISR quantum approximation for steadier increments.

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  67. Waveform stopped by runtime limit in iSR doesn't deinit the timer, bu… 

    …t stopWaveform refuses

to do anything if the waveform was stopped by runtime, either.
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  68. Improved quantum correction code.

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  69. Fix broken multi-wave generation.

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  70. Aggregate GPIO output across inner loop. True phase sync, and now bet… 

    …ter performance.
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  71. IRQ latency can be reduced from 2 to 1 us now, no WDT etc.

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  72. Improved handling of complete idle cycle miss, progress directly into… 

    … duty cycle.
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  73. Recalibrated after latest changes and reverts.

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  74. Overshoot compensation for duty cycle results in PWM milestone.

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  75. Adjustments to duty/idle cycle to mitigate effects of floating duty c… 

    …ycle logic.
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  76. Remove implicit condition from loop guard and fix timer restart duration

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  77. Host all static globals in an anonymous static struct.

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  78. Busy wait directly for next pending event and go to that pin.

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  79. Record nextEventCcy in waveform struct to save a few cycles.

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  80. Adapt duty cycle modification to only fix full duty and all idle cases.

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  81. Remember next pin to operate between IRQs.

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  82. Don't set pinMode each time on already running PWM or Tone.

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  83. Remove quantum, correct irq latency from testing,reuse isr timeout fr… 

    …om master et al
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  84. Move updating "now" out of inner loop, prevents float between pins th… 

    …at are in phase lock.
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  85. Merge init loop with action loop again.

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  86. Adaptive PWM frequency and floating duty cycle.

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  87. Predictive static frequency scaling.

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  88. Dynamic frequency down-scaling

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  89. Frequency scaling is only for PWM-like applications, anything needing… 

    … real time duty cycles or frequency must be able to fail on overload.
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  90. Conserve IRAM cache, resort to best effort.

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  91. Directly scale frequency for all duty/all idle waves to reasonable ma… 

    …ximum, reduces thrashing.
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  92. Getting the math right beats permanently reducing PWM frequency.

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  93. Rename identifier to help think about the problem.

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  94. AutoPwm correction moved to correct location - after overshoot recalc… 

    … - and allow limited duty floating
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  95. Finish overshoot math fixes.

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  96. First set pin mode, then digital write.

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  97. Simplify calculations, fix non-autoPwm for servo use, where exact dut… 

    …y is needed, idle is elastic.
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  98. Move wave initialization and modification outside the inner loop.

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  99. Some optimizing.

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  100. Updating "now" in the inner loop should lessen interference

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  101. Finally get rid of volatile and use atomic thread fence memory barrie… 

    …rs, great for ISR performance.
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  102. Improved idle cycle overshoot mitigation.

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  103. Improved duty cycle overshoot mitigation. 

    Case for investigation: 3% (shl 5) vs. 1.5% (shl 6), either less fuzz, but a few marked stray spots, or more fuzz, but no bumps in counter-PWM travel test.
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  104. Move startPin etc. into common static struct

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  105. Persist next event cycle across ISR invocations, like initPin was bef… 

    …ore.
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  106. Recalibrated DELTAIRQ and IRQLATENCY. Tested @ 3x 40kHz PWM + 440Hz Tone

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  107. CPU clock to Timer1 ccy correction must be dynamic even when BSP is c… 

    …ompiled for fixed CPU clock.
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  108. Corrected use of Timer1 registers and add rationale to Timer1 use in … 

    …comment.

Recalibrate for improved frequence downscaling @ 80MHz and 160MHz.
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  109. Let duty cycle overshoot correction depend on relative impact compare… 

    …ed to both period and duty.
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  110. 80MHz/160MHz specific code can be compile-time selected in general, o… 

    …nly NMI is affected by

apparent CPU frequency scaling in SDK code.
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  111. Seems that removing the redudant resetting of edge interrupt mode sha… 

    …ves 0.5us off rearm latency.
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  112. Recalibrated delta irq ccys.

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  113. Off-by-one in 100% duty overshoot correction.

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  114. Simple register writes.

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  115. Memory fences checked and joining events into same loop iteration tha… 

    …t are close to one another.
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  116. Shorten progression when going off 100% duty.

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  117. Code simplifications.

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  118. Dynamically map pins out from in-ISR handling based on next event tim… 

    …ing.

Major performance boost.
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  119. Reverting maximum IRQ period to 10ms. This sets the wave reprogrammin… 

    …g rate to 100Hz max.
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  120. Revert recent change that is the most likely cause of reported PWM fr… 

    …equency drop regression.
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  121. Much simplified overshoot mitigation code.

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  122. Fixing overshoot mitigation, 3x 880Hz, 256 states now.

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  123. Increase resolution by keeping reference time moving forward earlier.

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  124. Mitigation logic for ESP8266 SDK boosting to 160MHz during some WiFi … 

    …ops.
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  125. Event timestamps are all recorded for compile-time CPU frequency, the… 

    … timer ticks conversion

must be set at compile-time also. The SDK WiFi 160MHz boost mitigation temporarily handles
the CPU clock running twice as fast.
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  126. Expired pins must not be checked for next event.

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  127. Recalibrate after latest changes.

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  128. Save a few bytes code.

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  129. Guards are in place, so xor rather than and bitwise not.

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  130. Reduce memory use.

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  131. SDK boost to 160MHz may last across multiple ISR invocations, therefo… 

    …re adjust target ccy instead of ccount.
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  132. Overshoot mitigation w/o PWM frequency change.

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  133. New PWM overshoot mitigation code keeps frequency. Averages duty betw… 

    …een consecutive periods.
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  134. Small refactoring, remove code path that is never taken even at 3x25k… 

    …Hz/1023 PWM.
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  135. Don't ever skip off duty, no matter if late or infinitely short.

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  136. Shed speed-up code that didn't speed up things.

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  137. Must always recompute new waveform.nextEventCcy if there is any busy … 

    …pin.
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  138. Break out of ISR if timespan to next event allows, instead of busy wa… 

    …iting and stealing CPU cycles from userland.
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  139. Minor code simplification.

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  140. Improve code efficiency.

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  141. Improved performance of loop.

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  142. Recalibrated.

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  143. No positive effect of lead time inclusion was found during testing, r… 

    …emove this code.

Maximum period duration limit is implicit to timer, consider it documented constraint, don't runtime
check in ISR.
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  144. Fix WDT when at 160MHz CPU clock the Timer1 is set below 1µs.

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  145. Consolidate 160MHz constexpr check, finish 1µs minimum for Timer1 fix.

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  146. Test for non-zero before subtract should improve performance.

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  147. Reviewers/tested noted they were seeing WDT, and this change appeared… 

    … to fix that.
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  148. More expressive use of parentheses and alias CPU2X for reduced code s… 

    …ize.
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  149. Bug fix: at 160MHz compiled, don't force minimum Timer1 latency to 2µs.

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  150. Alternate CPU frequency scaling mitigation.

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  151. Handle time-of-flight in the right spot.

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  152. Remove _toneMap from Tone.cpp

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Commits on Nov 19, 2020

  1. Merge branch 'master' into waveform

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