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README.md
README.md
 
 
Sunum.pptx
Sunum.pptx
 
 
Teslim dokümanı.pdf
Teslim dokümanı.pdf
 
 
adder.sv
adder.sv
 
 
alu.sv
alu.sv
 
 
alu_control.sv
alu_control.sv
 
 
config.sv
config.sv
 
 
constants.sv
constants.sv
 
 
control_transfer.sv
control_transfer.sv
 
 
data_memory_interface.sv
data_memory_interface.sv
 
 
example_data_memory.sv
example_data_memory.sv
 
 
example_data_memory_bus.sv
example_data_memory_bus.sv
 
 
example_memory_bus.sv
example_memory_bus.sv
 
 
example_text_memory.sv
example_text_memory.sv
 
 
example_text_memory_bus.sv
example_text_memory_bus.sv
 
 
immediate_generator.sv
immediate_generator.sv
 
 
instruction_decoder.sv
instruction_decoder.sv
 
 
multiplexer.sv
multiplexer.sv
 
 
multiplexer2.sv
multiplexer2.sv
 
 
multiplexer4.sv
multiplexer4.sv
 
 
multiplexer8.sv
multiplexer8.sv
 
 
regfile.sv
regfile.sv
 
 
register.sv
register.sv
 
 
riscv_core.sv
riscv_core.sv
 
 
singlecycle_control.sv
singlecycle_control.sv
 
 
singlecycle_ctlpath.sv
singlecycle_ctlpath.sv
 
 
singlecycle_datapath.sv
singlecycle_datapath.sv
 
 
toplevel.sv
toplevel.sv
 
 

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RISC V Processor

RISC-V CPU is a design that can run 11 different operation codes written in system verilog language.

Results

When the developed RISC-V CPU processor meets the specified conditions, it can perform 11 commands and perform operations.
The advantages of the processor being based on risc-v have been seen.
It has been observed that the division of different units such as the constructor, the registers and the alu both accelerates and facilitates the project management.
As a result, the RISC-V CPU processor can properly perform the desired operations with machine language codes.

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Associated Projects

RTL Design of FB CPU

Circuit Design of FB CPU

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Processor with 11 operation codes based on RISC V

Topics

processor systemverilog risc-v

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