Add ch32v307 into 'devices.h' and some other changes

[COKPOWEHEU]

Add ch32v307 into 'devices.h', change page_size (1k -> 4k) and flash_size. For example in ch32v203rb flash is 224k, but cached (R0WAIT) only 128, 144 or 160 kbytes depending on USER option bits

[jmaselbas]

hi, thanks for submitting this pull-request.
I have some questions:

• why are you changing the flash_sector_size to 4096 ? I don't understand why.
• why are you using SZ_480K for all the flash size of the 0x17 32V30* device family ?

[COKPOWEHEU]

why are you changing the flash_sector_size to 1024 ?

From datasheet (4.3.9, table 4-18 for v307). I read that page_size (minimal programming size) is 256 bytes (except v003, v103 etc) and sector size is 4K (maximal erase size).

why are you using SZ_480K for all the flash size of the 0x17 32V30* device family ?

From datasheet: overview and 'model camparison' table, notes:
"Note: 1. Flash bytes represent zero-wait run area R0WAIT. For the V303/V305/V307 series, non-zero-wait area
is (480K-R0WAIT).
2. The products with 256K FLASH+64K SRAM support user select word to be configured as one of several
combinations of (192K FLASH+128K SRAM), (224K FLASH+96K SRAM), (256K FLASH+64K SRAM),
(288K FLASH+32K SRAM)."

As I understand these controllers has external flash chip (480K) and internal RAM that splits into program cache (192- 288K) and user RAM (32-128K).

[jmaselbas]

why are you changing the flash_sector_size to 1024 ?

From datasheet (4.3.9, table 4-18 for v307). I read that page_size (minimal programming size) is 256 bytes (except v003, v103 etc) and sector size is 4K (maximal erase size).

Ok, i've found the same info in the "CH32FV2x_V3x Reference Manual"

why are you using SZ_480K for all the flash size of the 0x17 32V30* device family ?

From datasheet: overview and 'model camparison' table, notes: "Note: 1. Flash bytes represent zero-wait run area R0WAIT. For the V303/V305/V307 series, non-zero-wait area is (480K-R0WAIT). 2. The products with 256K FLASH+64K SRAM support user select word to be configured as one of several combinations of (192K FLASH+128K SRAM), (224K FLASH+96K SRAM), (256K FLASH+64K SRAM), (288K FLASH+32K SRAM)."

As I understand these controllers has external flash chip (480K) and internal RAM that splits into program cache (192- 288K) and user RAM (32-128K).
Yes, this is can be configured with the SRAM_CODE_MODE in the "Option Byte Register" (FLASH_OBR)

From "CH32FV2x_V3x Reference Manual" sec 1.2.2 Memory allocation:

Built-in maximum 480 Kbytes of Flash program memory, for storing user applications.
...
Note: Memory allocaiton varies by model, refer to the corresponding datasheet of the chip for details.

I think there is at least two version, one with 480K and one with 224K, we can see this in "Figure 1-3 Storage mapping"

from http://www.jc-net.co.jp/pdf/CH32V307DS0-EN.pdf the CH32V303 V305 and V307, V208 series all have 480K of flash (aka Code Flash)

CH32V303 480K
CH32V305 480K
CH32V307 480K

CH32V203 224K
CH32V205 ? (likely the same as CH32F205) doesn't exists
CH32V207 ?
CH32V208 480K

CH32F203 224K
CH32F205 480K
CH32F207 480K
CH32F208 480K

It's very unclear to me what's the actual flash size. For instance the website doesn't advertise a flash size of 480K for CH32V307 but the datasheet does... it's confusing.

For the wch-isp use case the exact flash size doesn't really matter, it is only used to refuse to flash if the binary file is too big.

[jmaselbas]

I've create a new branch test_flash
can you give it a try ?

[COKPOWEHEU]

I tried my version on v307 before writing the pull-request. I have not another controllers yet.

[COKPOWEHEU]

Looks like I was wrong. In the 'rust' version, the sector size is always calculated at 1k. The GUI utility from WCH, also erases by 1k. For 792 byte firmware, 0x08 sectors are erased, for 12.5k - 0x0D.