s18: tile/obj banking (#686)

Some VDP priority issues are still exists
jotego · Jun 14, 2024 · 54fb5b3 · 54fb5b3
1 parent 3666b83
commit 54fb5b3
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Showing 4 changed files with 40 additions and 15 deletions.
diff --git a/cores/s18/cfg/mem.yaml b/cores/s18/cfg/mem.yaml
@@ -38,12 +38,12 @@ sdram:
     - { name: snd, addr_width: 21, data_width: 8 }
   # Bank 2 for tile graphics
   - buses:
-    - { name: char, addr_width: 14, data_width: 32, cs: gfx_cs }
+    - { name: char, addr_width: 22, data_width: 32, cs: gfx_cs }
     - { name: scr1, addr_width: 22, data_width: 32, cs: gfx_cs }
     - { name: scr2, addr_width: 22, data_width: 32, cs: gfx_cs }
   # Bank 3 objects
   - buses:
-    - { name: obj, addr_width: 21, data_width: 16 }
+    - { name: obj, addr_width: 23, data_width: 16 }
 
 bram:
   - name: pcm

diff --git a/cores/s18/hdl/jts18_game.v b/cores/s18/hdl/jts18_game.v
@@ -40,7 +40,7 @@ wire [23:1] cpu_addr;
 wire [15:0] char_dout, obj_dout, vdp_dout;
 wire [ 1:0] dsn, dswn;
 wire        UDSn, LDSn, main_rnw, vdp_dtackn;
-wire        char_cs, scr1_cs, pal_cs, objram_cs, asn;
+wire        char_cs, scr1_cs, pal_cs, objram_cs, bank_cs, asn;
 
 // Protection
 wire        key_we, mcu_we;
@@ -118,6 +118,7 @@ jts18_main u_main(
     .tile_bank  ( tile_bank ),
 
     // Video memory
+    .bank_cs    ( bank_cs   ),
     .vram_cs    ( vram_cs   ),
     .char_cs    ( char_cs   ),
     .pal_cs     ( pal_cs    ),
@@ -233,11 +234,12 @@ jts18_video u_video(
     .gray_n     ( gray_n    ),
     .tile_bank  ( tile_bank ),
 
-    // .game_id    ( game_id   ),
+    .game_id    ( game_id   ),
     // CPU interface
     .addr       ( cpu_addr  ),
     .char_cs    ( char_cs   ),
     .objram_cs  ( objram_cs ),
+    .bank_cs    ( bank_cs   ),
     .vint       ( vint      ),
     .dip_pause  ( dip_pause ),
 

diff --git a/cores/s18/hdl/jts18_main.v b/cores/s18/hdl/jts18_main.v
@@ -42,6 +42,7 @@ module jts18_main(
     output reg         char_cs,
     output reg         pal_cs,
     output reg         objram_cs,
+    output reg         bank_cs,
     input       [15:0] char_dout,
     input       [15:0] pal_dout,
     input       [15:0] obj_dout,
@@ -250,12 +251,12 @@ always @(posedge clk, posedge rst) begin
             pal_cs    <= active[REG_PAL];
             io_cs     <= active[REG_IO];
 
-
             // jtframe_ramrq requires cs to toggle to
             // process a new request. BUSn will toggle for
             // read-modify-writes
             vram_cs <= !BUSn && active[REG_VRAM] && !A[16];
             ram_cs  <= !BUSn && active[REG_RAM];
+            bank_cs <= (game_id[PCB_7525]|game_id[PCB_5987]|game_id[PCB_5987_DESERTBR]) && active[1] && !RnW;
         end else begin
             rom_cs    <= 0;
             char_cs   <= 0;
@@ -265,6 +266,7 @@ always @(posedge clk, posedge rst) begin
             vdp_cs    <= 0;
             vram_cs   <= 0;
             ram_cs    <= 0;
+            bank_cs   <= 0;
         end
     end
 end

diff --git a/cores/s18/hdl/jts18_video.v b/cores/s18/hdl/jts18_video.v
@@ -33,10 +33,12 @@ module jts18_video(
     input              vid16_en,
     input              gray_n,
     input      [ 7:0]  tile_bank,
+    input      [ 7:0]  game_id,
     output     [ 8:0]  vrender,
 
     // CPU interface
     input              dip_pause,
+    input              bank_cs,
     input              char_cs,
     input              objram_cs,
     input      [23:1]  addr,
@@ -58,7 +60,7 @@ module jts18_video(
 
     // SDRAM interface
     input              char_ok,
-    output     [13:2]  char_addr, // 9 addr + 3 vertical + 2 horizontal = 14 bits
+    output     [21:2]  char_addr, // 9 addr + 3 vertical + 2 horizontal = 14 bits
     input      [31:0]  char_data,
 
     input              map1_ok,
@@ -79,7 +81,7 @@ module jts18_video(
 
     input              obj_ok,
     output             obj_cs,
-    output     [20:1]  obj_addr,
+    output     [22:1]  obj_addr,
     input      [15:0]  obj_data,
 
     // Video signal
@@ -99,6 +101,13 @@ module jts18_video(
     output     [ 7:0]  st_dout
 );
 
+localparam       PCB_5874 = 0,  // refers to the bit in game_id
+                 PCB_5987_DESERTBR = 1,
+                 PCB_5987 = 2,
+                 PCB_7525 = 3,  // hamaway
+                 PCB_5873 = 4,  // lghost
+                 PCB_7248 = 5;  // shdancer
+
 wire [5:0] s16_r, s16_g, s16_b;
 wire [7:0] vdp_r, vdp_g, vdp_b;
 wire [7:0] st_s16, st_vdp;
@@ -109,12 +118,24 @@ wire       LHBL_dly, LVBL_dly, HS48, VS48, LHBL48, LVBL48,
            scr1_sel, scr2_sel, vdp_on,
            sa, sb, fix;
 wire [1:0] obj_prio;
+wire [2:0] scr1_bank, scr2_bank;
+wire [3:0] obj_bank;
+(* ramstyle = "logic" *) reg  [7:0] tilebanks[16];
+
+wire       alt_gfx = game_id[PCB_5987_DESERTBR]|game_id[PCB_5987]|game_id[PCB_7525];
+
+always @(posedge clk48)
+   if (bank_cs) tilebanks[addr[4:1]] <= game_id[PCB_7525] ? (din[7] ? {3'd0, din[4:0]} + 8'h20 : {3'd0, din[4:0]}) : din[7:0];
 
 assign st_dout = {3'd0, vdp_en, 3'd0,vdp_on};
-assign scr1_addr[21]=0;
-assign scr2_addr[21]=0;
-assign scr1_addr[20-:4] = scr1_sel ? tile_bank[7:4] : tile_bank[3:0];
-assign scr2_addr[20-:4] = scr2_sel ? tile_bank[7:4] : tile_bank[3:0];
+assign scr1_sel = scr1_bank[2];
+assign scr2_sel = scr2_bank[2];
+
+assign char_addr[21:14] = alt_gfx ? {tilebanks[0][6:0], 1'b0} : 8'd0;
+assign scr1_addr[21:15] = alt_gfx ? tilebanks[{1'b0, scr1_bank}][6:0] : {1'b0, scr1_sel ? tile_bank[7:4] : tile_bank[3:0], scr1_bank[1:0]};
+assign scr2_addr[21:15] = alt_gfx ? tilebanks[{1'b0, scr2_bank}][6:0] : {1'b0, scr2_sel ? tile_bank[7:4] : tile_bank[3:0], scr2_bank[1:0]};
+
+assign obj_addr[22:17] = (game_id[PCB_5987_DESERTBR]|game_id[PCB_5987]) ? {tilebanks[{1'b1, obj_bank[3:1]}][4:0], obj_bank[0]} : {2'd0, obj_bank};
 
 `ifndef NOVDP
 assign VS   = scr_vs;   // gfx_en[2] ? scr_vs   : vdp_vs;
@@ -164,28 +185,28 @@ jts18_video16 u_video16(
 
     // SDRAM interface
     .char_ok    ( char_ok   ),
-    .char_addr  ( char_addr ), // 9 addr + 3 vertical + 2 horizontal = 14 bits
+    .char_addr  ( char_addr[13:2] ), // 9 addr + 3 vertical + 2 horizontal = 14 bits
     .char_data  ( char_data ),
 
     .map1_ok    ( map1_ok   ),
     .map1_addr  ( map1_addr ), // 3 pages + 11 addr = 14 (32 kB)
     .map1_data  ( map1_data ),
 
     .scr1_ok    ( scr1_ok   ),
-    .scr1_addr  ({scr1_sel,scr1_addr[16:2]}), // 1 bank + 12 addr + 3 vertical = 15 bits
+    .scr1_addr  ({scr1_bank,scr1_addr[14:2]}), // 1 bank + 12 addr + 3 vertical = 15 bits
     .scr1_data  ( scr1_data ),
 
     .map2_ok    ( map2_ok   ),
     .map2_addr  ( map2_addr ), // 3 pages + 11 addr = 14 (32 kB)
     .map2_data  ( map2_data ),
 
     .scr2_ok    ( scr2_ok   ),
-    .scr2_addr  ({scr2_sel,scr2_addr[16:2]}), // 1 bank + 12 addr + 3 vertical = 15 bits
+    .scr2_addr  ({scr2_bank,scr2_addr[14:2]}), // 1 bank + 12 addr + 3 vertical = 15 bits
     .scr2_data  ( scr2_data ),
 
     .obj_ok     ( obj_ok    ),
     .obj_cs     ( obj_cs    ),
-    .obj_addr   ( obj_addr  ),
+    .obj_addr   ( {obj_bank, obj_addr[16:1]} ),
     .obj_data   ( obj_data  ),
 
     // Video signal