s18 wip

jotego · Apr 21, 2024 · e63a12e · e63a12e
1 parent a147b1e
commit e63a12e
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Showing 4 changed files with 84 additions and 5 deletions.
diff --git a/cores/s18/cfg/macros.def b/cores/s18/cfg/macros.def
@@ -7,4 +7,20 @@ JTFRAME_BA3_START=0x0702000
 JTFRAME_HEADER=32
 
 # move along nothing to see here
-JTFRAME_SKIP
+JTFRAME_SKIP
+
+# Game codes
+# 5874
+GAME_ASTORM  =0x01
+GAME_BLOXEED =0x01
+GAME_MWALK   =0x01
+GAME_PONTOON =0x01
+# 5987
+GAME_CLTCHITR=0x04
+GAME_DESERTBT=0x04
+GAME_DDCREW  =0x04
+# single game
+GAME_HAMAWAY =0x08
+GAME_LGHOST  =0x10
+GAME_SHDANCER=0x20
+GAME_WWALLY  =0x40
diff --git a/cores/s18/cfg/mame2mra.toml b/cores/s18/cfg/mame2mra.toml
@@ -31,6 +31,18 @@ data = [
     { offset=0x11, dev="fd1094",  data="01" },
     { offset=0x12, dev="mc8123",  data="01" },
     { offset=0x13, dev="i8751",   data="01" },
+
+    # 5874 board
+    { machines=["astorm", "bloxeed", "mwalk", "pontoon"],  offset=0x18, data="01" },
+    # 5987 board
+    # ddcrewu, ddcrew1, ddcrewj might be different
+    { machines=["cltchitr", "desertbr", "ddcrew"], offset=0x18, data="17" },
+    # single-game boards
+    { machine="hamaway",  offset=0x18, data="17" },
+    { machine="lghost",   offset=0x18, data="17" },
+    { machine="shdancer", offset=0x18, data="17" },
+    # wwally's machine may be in a different MAME file, not segas18
+    { machine="wwally",   offset=0x18, data="17" },
 ]
 
 [ROM]

diff --git a/cores/s18/hdl/jts18b_main.v → cores/s18/hdl/jts18_main.v b/cores/s18/hdl/jts18b_main.v → cores/s18/hdl/jts18_main.v
@@ -16,7 +16,7 @@
     Version: 1.0
     Date: 5-7-2021 */
 
-module jts18b_main(
+module jts18_main(
     input              rst,
     input              clk,
     input              rst24,
@@ -305,8 +305,7 @@ jtframe_8751mcu #(
     .prom_we    ( mcu_prog_we   )
 );
 
-
-// System 16B memory map
+// System 18 memory map
 always @(posedge clk, posedge rst) begin
     if( rst ) begin
             rom_cs    <= 0;

diff --git a/cores/s18/hdl/jts18_sound.v b/cores/s18/hdl/jts18_sound.v
@@ -24,6 +24,13 @@ module jts18_sound(
     input                cen_pcm,   // 10 MHz
     input                nmi_n,     // from mapper
 
+    // Mapper device 315-5195
+    output               mapper_rd,
+    output               mapper_wr,
+    output [7:0]         mapper_din,
+    input  [7:0]         mapper_dout,
+    input                mapper_pbf, // pbf signal == buffer full ?
+
     // PROM
     input         [ 9:0] prog_addr,
     input                prom_we,
@@ -47,7 +54,52 @@ wire [ 7:0] dout, ram_dout;
 reg  [ 7:0] din;
 reg         ram_cs, rom_cs;
 
-assign io_wrn = iorq_n | wr_n;
+assign io_wrn     = iorq_n | wr_n;
+assign mapper_rd  = mapper_cs && !rd_n;
+assign mapper_wr  = mapper_cs && !wr_n;
+assign mapper_din = cpu_dout;
+
+// ROM bank address
+always @(*) begin
+    rom_addr = { 4'd0, A[14:0] };
+    if( bank_cs ) begin
+        rom_addr[15:14] = rom_msb[1:0];
+        casez( ~rom_msb[5:2] ) // A11-A8 refer to the ROM label in the PCB:
+            4'b1000: rom_addr[17:16] = 3; // A11 at top
+            4'b0100: rom_addr[17:16] = 2; // A10
+            4'b0010: rom_addr[17:16] = 1; // A9
+            4'b0001: rom_addr[17:16] = 0; // A8
+            default: rom_addr[17:16] = 0;
+        endcase
+            default: // 5521 & 5704
+                rom_addr[17:14] = rom_msb[3:0];
+        endcase
+        rom_addr = rom_addr + 19'h10000;
+    end
+end
+
+wire underA = A[15:12]<4'ha;
+wire underC = A[15:12]<4'hc;
+
+always @(*) begin
+    ram_cs  = !mreq_n && &A[15:13];
+    bank_cs = !mreq_n && (!underA && underC);
+    pcm_cs  = !mreq_n && (!underC && A[15:12]<4'he);
+    rom_cs  = !mreq_n &&   underC;
+
+    // Port Map
+    { fm0_cs, fm1_cs, breg_cs, mapper_cs } = 0;
+    if( !iorq_n && m1_n ) begin
+        case( A[7:4] )
+            4'h8: fm0_cs    = 1;
+            4'h9: fm1_cs    = 1;
+            4'ha: breg_cs   = 1;
+            4'hc: mapper_cs = 1;
+            default:;
+        endcase
+    end
+end
+
 
 jt12 u_fm0(
     .rst        ( rst           ),