This is our version of a system bus architecture, custom built with a selection of custom protocols.
The design has been inspired by the design and functionality of the AMBA Spec 2.0, AHB/APB buses. Hence it consists of a blend of characteristics native to those bus arcitectures, albeit with significant performance and functionality limitations.
A more detailed report on the performance is available here.
| Features | Design Limitations |
|---|---|
| Priority requests | Data transfers limited to 32-bit WORD sized packets |
| Write / read transactions | No burst transfer capability |
| Split transactions | Split transactions only possible on READ operations |
| Designed around a specfied static clock frequency |
Master | Slave States
The figures above show a brief glimpse of a SPLIT transaction taking place between Master 1 and Slave 1. Bus access is handed off to Master 2 and Slave 2 to perform a WRITE operation in the intermittent time duration. More details included in report.
The entire codebase was written and synthesized in Xilinx ISE Design Suite 14.7.
All waveform simulations were performed in the integrated ISim platform.
ARM Developer Documentation : AMBA Specification (Rev 2.0)